Investigation on the mechanism of the leakage failure between poly gate and contact in subnano technology

Q. F. Wang; S. L. Toh; Q. Deng; P. K. Tan; K. Li; J. Teong; Z. H. Mai; J. Lam

doi:10.1109/IPFA.2008.4588159

Investigation on the mechanism of the leakage failure between poly gate and contact in subnano technology

Q. F. Wang, S. L. Toh, Q. Deng, P. K. Tan, K. Li, J. Teong, Z. H. Mai, J. Lam

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

With the shrinkage of the transistor dimensions, the spacing between the structures become smaller and smaller. However due to the intrinsic characteristic of the CMOS device, the reduction of the operating voltage is limited. The electrical field between different structures keeps on increasing with the shrinkage of the transistor dimensions. Furthermore, many new failure modes were observed with the scaling of semiconductor device. One of them is poly gate to contact leakage. In this paper, the mechanism of the leakage failure between poly gate and the contact in subnano CMOS technology was discussed.

Original language	English (US)
Title of host publication	2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
DOIs	https://doi.org/10.1109/IPFA.2008.4588159
State	Published - 2008
Externally published	Yes
Event	2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA - Singapore, Singapore Duration: Jul 7 2008 → Jul 11 2008

Publication series

Name	Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Other

Other	2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA
Country/Territory	Singapore
City	Singapore
Period	07/7/08 → 07/11/08

ASJC Scopus subject areas

General Engineering

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10.1109/IPFA.2008.4588159

Cite this

Wang, Q. F., Toh, S. L., Deng, Q., Tan, P. K., Li, K., Teong, J., Mai, Z. H., & Lam, J. (2008). Investigation on the mechanism of the leakage failure between poly gate and contact in subnano technology. In 2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA Article 4588159 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). https://doi.org/10.1109/IPFA.2008.4588159

Wang, Q. F. ; Toh, S. L. ; Deng, Q. et al. / Investigation on the mechanism of the leakage failure between poly gate and contact in subnano technology. 2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA. 2008. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

@inproceedings{2139bef3282d4d5ebd73fa6f78b65211,

title = "Investigation on the mechanism of the leakage failure between poly gate and contact in subnano technology",

abstract = "With the shrinkage of the transistor dimensions, the spacing between the structures become smaller and smaller. However due to the intrinsic characteristic of the CMOS device, the reduction of the operating voltage is limited. The electrical field between different structures keeps on increasing with the shrinkage of the transistor dimensions. Furthermore, many new failure modes were observed with the scaling of semiconductor device. One of them is poly gate to contact leakage. In this paper, the mechanism of the leakage failure between poly gate and the contact in subnano CMOS technology was discussed.",

author = "Wang, {Q. F.} and Toh, {S. L.} and Q. Deng and Tan, {P. K.} and K. Li and J. Teong and Mai, {Z. H.} and J. Lam",

year = "2008",

doi = "10.1109/IPFA.2008.4588159",

language = "English (US)",

isbn = "1424420393",

series = "Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA",

booktitle = "2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA",

note = "2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA ; Conference date: 07-07-2008 Through 11-07-2008",

}

Wang, QF, Toh, SL, Deng, Q, Tan, PK, Li, K, Teong, J, Mai, ZH & Lam, J 2008, Investigation on the mechanism of the leakage failure between poly gate and contact in subnano technology. in 2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA., 4588159, Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, 2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA, Singapore, Singapore, 07/7/08. https://doi.org/10.1109/IPFA.2008.4588159

Investigation on the mechanism of the leakage failure between poly gate and contact in subnano technology. / Wang, Q. F.; Toh, S. L.; Deng, Q. et al.
2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA. 2008. 4588159 (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Li, K.

AU - Teong, J.

AU - Mai, Z. H.

AU - Lam, J.

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N2 - With the shrinkage of the transistor dimensions, the spacing between the structures become smaller and smaller. However due to the intrinsic characteristic of the CMOS device, the reduction of the operating voltage is limited. The electrical field between different structures keeps on increasing with the shrinkage of the transistor dimensions. Furthermore, many new failure modes were observed with the scaling of semiconductor device. One of them is poly gate to contact leakage. In this paper, the mechanism of the leakage failure between poly gate and the contact in subnano CMOS technology was discussed.

AB - With the shrinkage of the transistor dimensions, the spacing between the structures become smaller and smaller. However due to the intrinsic characteristic of the CMOS device, the reduction of the operating voltage is limited. The electrical field between different structures keeps on increasing with the shrinkage of the transistor dimensions. Furthermore, many new failure modes were observed with the scaling of semiconductor device. One of them is poly gate to contact leakage. In this paper, the mechanism of the leakage failure between poly gate and the contact in subnano CMOS technology was discussed.

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M3 - Conference contribution

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T3 - Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

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ER -

Wang QF, Toh SL, Deng Q, Tan PK, Li K, Teong J et al. Investigation on the mechanism of the leakage failure between poly gate and contact in subnano technology. In 2008 15th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA. 2008. 4588159. (Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA). doi: 10.1109/IPFA.2008.4588159

Investigation on the mechanism of the leakage failure between poly gate and contact in subnano technology

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