Interpolation based direct digital frequency synthesis for wireless communications

Ahmed M. Eltawil; Babak Daneshrad

doi:10.1109/WCNC.2002.993466

Interpolation based direct digital frequency synthesis for wireless communications

Ahmed M. Eltawil, Babak Daneshrad

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

14 Scopus citations

Abstract

In this paper, a compact architecture for direct digital frequency synthesis (DDFS) is presented. It uses a smaller lookup table for sine and cosine functions compared to existing architectures, with minimal hardware overhead. The computation of the sinusoidal values is performed by a parabolic interpolation structure, thus only interpolation coefficients need to be stored in the read-only memory (ROM). A DDFS with 64 dBc SFDR, 10-bit output resolution and 32 bit phase accumulator requires only 104 bits of ROM storage. The ROM size is consistently less than 1 Kbits for SFDR up to 85 dBc.

Original language	English (US)
Title of host publication	IEEE Wireless Communications and Networking Conference, WCNC
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Print)	0780373766
DOIs	https://doi.org/10.1109/WCNC.2002.993466
State	Published - Jan 1 2002
Externally published	Yes

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Generated from Scopus record by KAUST IRTS on 2019-11-20

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10.1109/WCNC.2002.993466

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title = "Interpolation based direct digital frequency synthesis for wireless communications",

abstract = "In this paper, a compact architecture for direct digital frequency synthesis (DDFS) is presented. It uses a smaller lookup table for sine and cosine functions compared to existing architectures, with minimal hardware overhead. The computation of the sinusoidal values is performed by a parabolic interpolation structure, thus only interpolation coefficients need to be stored in the read-only memory (ROM). A DDFS with 64 dBc SFDR, 10-bit output resolution and 32 bit phase accumulator requires only 104 bits of ROM storage. The ROM size is consistently less than 1 Kbits for SFDR up to 85 dBc.",

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Y1 - 2002/1/1

N2 - In this paper, a compact architecture for direct digital frequency synthesis (DDFS) is presented. It uses a smaller lookup table for sine and cosine functions compared to existing architectures, with minimal hardware overhead. The computation of the sinusoidal values is performed by a parabolic interpolation structure, thus only interpolation coefficients need to be stored in the read-only memory (ROM). A DDFS with 64 dBc SFDR, 10-bit output resolution and 32 bit phase accumulator requires only 104 bits of ROM storage. The ROM size is consistently less than 1 Kbits for SFDR up to 85 dBc.

AB - In this paper, a compact architecture for direct digital frequency synthesis (DDFS) is presented. It uses a smaller lookup table for sine and cosine functions compared to existing architectures, with minimal hardware overhead. The computation of the sinusoidal values is performed by a parabolic interpolation structure, thus only interpolation coefficients need to be stored in the read-only memory (ROM). A DDFS with 64 dBc SFDR, 10-bit output resolution and 32 bit phase accumulator requires only 104 bits of ROM storage. The ROM size is consistently less than 1 Kbits for SFDR up to 85 dBc.

UR - http://ieeexplore.ieee.org/document/993466/

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U2 - 10.1109/WCNC.2002.993466

DO - 10.1109/WCNC.2002.993466

M3 - Conference contribution

SN - 0780373766

BT - IEEE Wireless Communications and Networking Conference, WCNC

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Interpolation based direct digital frequency synthesis for wireless communications

Abstract

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