@inproceedings{7b24f1229e134ca4bc88b32bd00b3b26,
title = "Integration challenges and opportunities for nanometer scale dual metal gate CMOSFET",
abstract = "As MOSFET scales below 45nm, conventional SiO2 cannot sustain equivalent oxide thickness (EOT) and leakage current requirements set in the International Technology Roadmap for Semiconductors (ITRS), due to the limitation of physical-thickness scaling, and high tunneling current [1]. Metal gate and high-k dielectric have been extensively studied to overcome the limitation of conventional poly gate and SiO2 technology. Although recent advancements of the technology enable the metal gate and high-k dielectric to be implemented in actual manufacturing, several issues remain associated with integrating the new materials in CMOS field-effect transistors (FETs). This paper will introduce various integration schemes for fabricating dual metal gate CMOSFET, and review pros and cons of each approach to propose general integration guide for the desired application.",
author = "Song, {S. C.} and M. Hussain and J. Barnett and Park, {C. S.} and C. Park and P. Kirsch and Lee, {B. H.} and R. Jammy",
year = "2007",
doi = "10.1149/1.2778389",
language = "English (US)",
isbn = "9781566775724",
series = "ECS Transactions",
publisher = "Electrochemical Society Inc.",
number = "6",
pages = "315--329",
booktitle = "ECS Transactions - 5th International Symposium on ULSI Process Integration",
edition = "6",
note = "5th International Symposium on ULSI Process Integration - 212th ECS Meeting ; Conference date: 07-10-2007 Through 12-10-2007",
}