Integrating dual workfunction metal gates in CMOS

As MOSFET scales below 45nm, conventional SiO₂ cannot sustain equivalent oxide thickness (EOT) and leakage current requirements set in the International Technology Roadmap for Semiconductors (ITRS), due to the limitation of physical-thickness scaling, and high tunneling current [1]. Dual metal gate CMOS integration requires several wet etch processes to separate two different metal gates within transistors on the same wafer. Integration schemes as well as wet etch chemistries must be developed to completely remove the first metal gate without damaging the underlying gate dielectric. Hardmask material to selectively mask the first metal gate must be chosen carefully, since the hardmask is removed when the gate dielectric is exposed in certain integration schemes. This paper will introduce various integration schemes for fabricating dual metal gate CMOS field-effect transistors (FETs).