Improving effective yield through error tolerant system design

Ahmed M. Eltawil, Fadi J. Kurdahi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

12 Scopus citations


This paper illustrates that the effective chip yield (memory) can be improved up to 10x by incorporating error tolerance in the system design rather than incorporating design for yield at the circuit stage. The proposed approach leverages the fact that some applications - by construction - are inherently error tolerant and therefore do not require a strict bound of 100% correctness to function. This concept is elaborated upon using a wireless communication system framework as a case study for application aware yield enhancement.
Original languageEnglish (US)
Title of host publicationProceedings of the IEEE International Conference on Electronics, Circuits, and Systems
StatePublished - Dec 1 2005
Externally publishedYes

Bibliographical note

Generated from Scopus record by KAUST IRTS on 2019-11-20


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