TY - GEN
T1 - Improved StrongARM latch comparator: Design, analysis and performance evaluation
AU - Almansouri, Abdullah Saud Mohammed
AU - Al-Turki, Abdullah Turki
AU - Alshehri, Abdullah
AU - Al Attar, Talal
AU - Al Attar, Talal
AU - Fariborzi, Hossein
N1 - KAUST Repository Item: Exported on 2020-10-01
PY - 2017/7/13
Y1 - 2017/7/13
N2 - This paper presents an improved StrongARM latch comparator, designed and simulated in 90nm and 32nm CMOS technologies. The proposed design provides an improvement of 7% in energy efficiency, 14% in speed and an average reduction of 41% in the clock feedthrough, compared to the conventional design. The new architecture also minimizes the area by reducing the required transistors needed for the enhanced performance.
AB - This paper presents an improved StrongARM latch comparator, designed and simulated in 90nm and 32nm CMOS technologies. The proposed design provides an improvement of 7% in energy efficiency, 14% in speed and an average reduction of 41% in the clock feedthrough, compared to the conventional design. The new architecture also minimizes the area by reducing the required transistors needed for the enhanced performance.
UR - http://hdl.handle.net/10754/625683
UR - http://ieeexplore.ieee.org/document/7974114/
UR - http://www.scopus.com/inward/record.url?scp=85027542743&partnerID=8YFLogxK
U2 - 10.1109/PRIME.2017.7974114
DO - 10.1109/PRIME.2017.7974114
M3 - Conference contribution
SN - 9781509065080
SP - 89
EP - 92
BT - 2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)
PB - Institute of Electrical and Electronics Engineers (IEEE)
ER -