Improved circuit model for all-spin logic

Meshal Alawein; Hossein Fariborzi

doi:10.1145/2950067.2950075

Improved circuit model for all-spin logic

Meshal Alawein, Hossein Fariborzi

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

Spintronic devices are prime candidates for Beyond CMOS era due to their potential for low power consumption and high density computation and storage. All-spin logic (ASL) is among the most promising spintronic logic switches. Previous attempts to model ASL in the linear and diffusive regime either neglect the dynamic characteristics of the transport or do not provide a scalable and robust platform for full micromagnetic simulations and inclusion of other effects like spin Hall effect (SHE) and spin-orbit torque (SOT). In this paper, and based on a finite difference scheme, we propose an improved self-consisting magnetization dynamics/time-dependent carrier transport model that captures the main characteristics of ASL devices.

Original language	English (US)
Title of host publication	Proceedings of the 2016 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2016
Publisher	Presses Polytechniques Et Universitaires Romandes
Pages	135-140
Number of pages	6
ISBN (Electronic)	9781450343305
DOIs	https://doi.org/10.1145/2950067.2950075
State	Published - Sep 14 2016
Event	2016 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2016 - Beijing, China Duration: Jul 18 2016 → Jul 20 2016

Publication series

Name	Proceedings of the 2016 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2016

Conference

Conference	2016 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2016
Country/Territory	China
City	Beijing
Period	07/18/16 → 07/20/16

Bibliographical note

Publisher Copyright:
© 2016 ACM.

ASJC Scopus subject areas

Electrical and Electronic Engineering
Hardware and Architecture

Access to Document

10.1145/2950067.2950075

Cite this

Alawein, M., & Fariborzi, H. (2016). Improved circuit model for all-spin logic. In Proceedings of the 2016 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2016 (pp. 135-140). Article 7568640 (Proceedings of the 2016 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2016). Presses Polytechniques Et Universitaires Romandes. https://doi.org/10.1145/2950067.2950075

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Alawein, M & Fariborzi, H 2016, Improved circuit model for all-spin logic. in Proceedings of the 2016 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2016., 7568640, Proceedings of the 2016 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2016, Presses Polytechniques Et Universitaires Romandes, pp. 135-140, 2016 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2016, Beijing, China, 07/18/16. https://doi.org/10.1145/2950067.2950075

Improved circuit model for all-spin logic. / Alawein, Meshal; Fariborzi, Hossein.
Proceedings of the 2016 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2016. Presses Polytechniques Et Universitaires Romandes, 2016. p. 135-140 7568640 (Proceedings of the 2016 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Alawein M, Fariborzi H. Improved circuit model for all-spin logic. In Proceedings of the 2016 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2016. Presses Polytechniques Et Universitaires Romandes. 2016. p. 135-140. 7568640. (Proceedings of the 2016 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2016). doi: 10.1145/2950067.2950075

Improved circuit model for all-spin logic

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