TY - GEN
T1 - Implementing DSP algorithms with on-chip networks
AU - Wu, Xiang
AU - Ragheb, Tamer
AU - Aziz, Adnan
AU - Massoud, Yehia
N1 - Generated from Scopus record by KAUST IRTS on 2022-09-13
PY - 2007/11/29
Y1 - 2007/11/29
N2 - Many DSP algorithms are very computationally intensive. They are typically implemented using an ensemble of processing elements (PEs) operating inparallel. The results from PEs need to be communicated with other PEs, and for many applications the cost of implementing the communication between PEs is very high. Given a DSP algorithm with high communication complexity, it is natural to use a Network-on-Chip (NoC) to implement the communication. We address two key optimization problems that arise in this context - placement, i.e., assigning computations to PEs on the NoC, and scheduling, i.e., constructing a detailed cycle-by-cycle scheme for implementing the communication between PEs on the NoC. © 2007 IEEE.
AB - Many DSP algorithms are very computationally intensive. They are typically implemented using an ensemble of processing elements (PEs) operating inparallel. The results from PEs need to be communicated with other PEs, and for many applications the cost of implementing the communication between PEs is very high. Given a DSP algorithm with high communication complexity, it is natural to use a Network-on-Chip (NoC) to implement the communication. We address two key optimization problems that arise in this context - placement, i.e., assigning computations to PEs on the NoC, and scheduling, i.e., constructing a detailed cycle-by-cycle scheme for implementing the communication between PEs on the NoC. © 2007 IEEE.
UR - http://ieeexplore.ieee.org/document/4209025/
UR - http://www.scopus.com/inward/record.url?scp=36348968265&partnerID=8YFLogxK
U2 - 10.1109/NOCS.2007.25
DO - 10.1109/NOCS.2007.25
M3 - Conference contribution
SN - 0769527736
SP - 307
EP - 316
BT - Proceedings - NOCS 2007: First International Symposium on Networks-on-Chip
ER -