Implementing DSP algorithms with on-chip networks

Xiang Wu, Tamer Ragheb, Adnan Aziz, Yehia Massoud

Research output: Chapter in Book/Report/Conference proceedingConference contribution

22 Scopus citations


Many DSP algorithms are very computationally intensive. They are typically implemented using an ensemble of processing elements (PEs) operating inparallel. The results from PEs need to be communicated with other PEs, and for many applications the cost of implementing the communication between PEs is very high. Given a DSP algorithm with high communication complexity, it is natural to use a Network-on-Chip (NoC) to implement the communication. We address two key optimization problems that arise in this context - placement, i.e., assigning computations to PEs on the NoC, and scheduling, i.e., constructing a detailed cycle-by-cycle scheme for implementing the communication between PEs on the NoC. © 2007 IEEE.
Original languageEnglish (US)
Title of host publicationProceedings - NOCS 2007: First International Symposium on Networks-on-Chip
Number of pages10
StatePublished - Nov 29 2007
Externally publishedYes

Bibliographical note

Generated from Scopus record by KAUST IRTS on 2022-09-13


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