TY - GEN
T1 - Impact of process variations on carbon nanotube bundle interconnect for future FPGA architectures
AU - Eachempati, S.
AU - Vijaykrishnan, N.
AU - Nieuwoudt, Arthur
AU - Massoud, Yehia
N1 - Generated from Scopus record by KAUST IRTS on 2022-09-13
PY - 2007/11/28
Y1 - 2007/11/28
N2 - As CMOS technology continues to scale, copper interconnect (CuI) will hinder the performance and reliability of Field Programmable Gate Arrays (FPGA) motivating the need for alternative interconnect solutions for future process technologies. In this paper, we investigate the impact of statistical variations in interconnect properties on FPGA timing yield (TY) when bundles of single-walled carbon nanotubes (SWCNT) are used as interconnect in the FPGA routing fabric. The results indicate that SWCNT bundle-based interconnect (SWCNTBI) can provide a superior performance-yield trade-off over FPGAs implemented using traditional CuI in future process technologies. © 2007 IEEE.
AB - As CMOS technology continues to scale, copper interconnect (CuI) will hinder the performance and reliability of Field Programmable Gate Arrays (FPGA) motivating the need for alternative interconnect solutions for future process technologies. In this paper, we investigate the impact of statistical variations in interconnect properties on FPGA timing yield (TY) when bundles of single-walled carbon nanotubes (SWCNT) are used as interconnect in the FPGA routing fabric. The results indicate that SWCNT bundle-based interconnect (SWCNTBI) can provide a superior performance-yield trade-off over FPGAs implemented using traditional CuI in future process technologies. © 2007 IEEE.
UR - http://ieeexplore.ieee.org/document/4208978/
UR - http://www.scopus.com/inward/record.url?scp=36348999644&partnerID=8YFLogxK
U2 - 10.1109/ISVLSI.2007.56
DO - 10.1109/ISVLSI.2007.56
M3 - Conference contribution
SN - 0769528961
SP - 516
EP - 517
BT - Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures
ER -