Impact of Physical Stress on Gate Dielectric in Ultrathin Si Gate-Stack for Next-Generation Flexible CMOS Technology

In this article, we report the fabrication and characterizations of sub-20- μm thin flexible Si die containing active devices. Thermally grown 2.62-nm silicon dioxide (SiO₂), atomic layer deposition (ALD)-deposited 3-nm HfO₂ (high-κ), and 10-nm TiN layers are used to fabricate an array of MOSCAPs on Si wafers. The fabricated devices are characterized to analyze the doping density (N_a ), flat-band voltage (V_fb), threshold voltage (V_th ), fixed oxide charge (Q_f), and interface trap densities (D_it). Then, a deep reactive ion etching (DRIE) reduces the die thickness to ˜ 15μm for flexibility. The encapsulated flexible devices are found to have relatively better breakdown performances when tested in compressive stressing and no variations when in tensile stress. The time-dependent dielectric breakdown (TDDB) measurement shows a minimal variation in flexible and bulk devices. The TDDB and a voltage acceleration slope are projected in flexible devices after performing a 10000 times bending and relaxation process (cycling).