Impact of dummy filling techniques on interconnect capacitance and planarization in nano-scale process technology

Arthur Nieuwoudt, Jamil Kawa, Yehia Massoud

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Scopus citations

Abstract

As process technology continues to scale into the nanometer regime, the interplay between dummy fill metal placement and interconnect thickness variation due to chemical mechanical polishing (CMP) has become increasingly important for performance, reliability, and yield. This paper provides the first simultaneous investigation of both the interconnect capacitance increases and the CMP-induced thickness variations associated with rule-based and model-based fill generation methods. The results indicate that dummy fill can have a significant impact on both parasitic capacitance and interconnect planarization for large-scale designs implemented in 65 nm technology. We also demonstrate that model-based methods can simultaneously provide smaller incremental capacitance increases and better interconnect planarization compared to rule-based techniques. Copyright 2008 ACM.
Original languageEnglish (US)
Title of host publicationProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
Pages151-154
Number of pages4
DOIs
StatePublished - Dec 1 2008
Externally publishedYes

Bibliographical note

Generated from Scopus record by KAUST IRTS on 2022-09-13

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