TY - GEN
T1 - Impact of dummy filling techniques on interconnect capacitance and planarization in nano-scale process technology
AU - Nieuwoudt, Arthur
AU - Kawa, Jamil
AU - Massoud, Yehia
N1 - Generated from Scopus record by KAUST IRTS on 2022-09-13
PY - 2008/12/1
Y1 - 2008/12/1
N2 - As process technology continues to scale into the nanometer regime, the interplay between dummy fill metal placement and interconnect thickness variation due to chemical mechanical polishing (CMP) has become increasingly important for performance, reliability, and yield. This paper provides the first simultaneous investigation of both the interconnect capacitance increases and the CMP-induced thickness variations associated with rule-based and model-based fill generation methods. The results indicate that dummy fill can have a significant impact on both parasitic capacitance and interconnect planarization for large-scale designs implemented in 65 nm technology. We also demonstrate that model-based methods can simultaneously provide smaller incremental capacitance increases and better interconnect planarization compared to rule-based techniques. Copyright 2008 ACM.
AB - As process technology continues to scale into the nanometer regime, the interplay between dummy fill metal placement and interconnect thickness variation due to chemical mechanical polishing (CMP) has become increasingly important for performance, reliability, and yield. This paper provides the first simultaneous investigation of both the interconnect capacitance increases and the CMP-induced thickness variations associated with rule-based and model-based fill generation methods. The results indicate that dummy fill can have a significant impact on both parasitic capacitance and interconnect planarization for large-scale designs implemented in 65 nm technology. We also demonstrate that model-based methods can simultaneously provide smaller incremental capacitance increases and better interconnect planarization compared to rule-based techniques. Copyright 2008 ACM.
UR - http://portal.acm.org/citation.cfm?doid=1366110.1366148
UR - http://www.scopus.com/inward/record.url?scp=54249160044&partnerID=8YFLogxK
U2 - 10.1145/1366110.1366148
DO - 10.1145/1366110.1366148
M3 - Conference contribution
SN - 9781595939999
SP - 151
EP - 154
BT - Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
ER -