High Throughput Spatial Convolution Filters on FPGAs

Lenos Ioannou, Abdullah Al-Dujaili, Suhaib A. Fahmy

Research output: Contribution to journalArticlepeer-review

5 Scopus citations


Digital signal processing (DSP) on field-programmable gate arrays (FPGAs) has long been appealing because of the inherent parallelism in these computations that can be easily exploited to accelerate such algorithms. FPGAs have evolved significantly to further enhance the mapping of these algorithms, included additional hard blocks, such as the DSP blocks found in modern FPGAs. Although these DSP blocks can offer more efficient mapping of DSP computations, they are primarily designed for 1-D filter structures. We present a study on spatial convolutional filter implementations on FPGAs, optimizing around the structure of the DSP blocks to offer high throughput while maintaining the coefficient flexibility that other published architectures usually sacrifice. We show that it is possible to implement large filters for large 4K resolution image frames at frame rates of 30-60 FPS, while maintaining functional flexibility.
Original languageEnglish (US)
Pages (from-to)1392-1402
Number of pages11
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number6
StatePublished - Jun 1 2020
Externally publishedYes

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Generated from Scopus record by KAUST IRTS on 2021-03-16


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