High throughput accelerator interface framework for a linear time-multiplexed FPGA overlay

Xiangwei Li; Kizheppatt Vipin; Douglas L. Maskell; Suhaib A. Fahmy; Abhishek Kumar Jain

High throughput accelerator interface framework for a linear time-multiplexed FPGA overlay

Xiangwei Li^*, Kizheppatt Vipin, Douglas L. Maskell, Suhaib A. Fahmy, Abhishek Kumar Jain

^*Corresponding author for this work

Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

Coarse-grained FPGA overlays improve design productivity through software-like programmability and fast compilation. However, the effectiveness of overlays as accelerators is dependent on suitable interface and programming integration into a typically processor-based computing system, an aspect which has often been neglected in evaluations of overlays. We explore the integration of a time-multiplexed FPGA overlay over a server-class PCI Express interface. We show how this integration can be optimised to maximise performance, and evaluate the area overhead. We also propose a user-friendly programming model for such an overlay accelerator system.

Original language	English (US)
Title of host publication	2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728133201
State	Published - 2020
Event	52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Virtual, Online Duration: Oct 10 2020 → Oct 21 2020

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2020-October
ISSN (Print)	0271-4310

Conference

Conference	52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020
City	Virtual, Online
Period	10/10/20 → 10/21/20

Bibliographical note

Publisher Copyright:
© 2020 IEEE

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

Li, X., Vipin, K., Maskell, D. L., Fahmy, S. A., & Jain, A. K. (2020). High throughput accelerator interface framework for a linear time-multiplexed FPGA overlay. In 2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings Article 9181072 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2020-October). Institute of Electrical and Electronics Engineers Inc..

Li, Xiangwei ; Vipin, Kizheppatt ; Maskell, Douglas L. et al. / High throughput accelerator interface framework for a linear time-multiplexed FPGA overlay. 2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2020. (Proceedings - IEEE International Symposium on Circuits and Systems).

@inproceedings{7dca3b05c7c64e478a1decb41d37bc80,

title = "High throughput accelerator interface framework for a linear time-multiplexed FPGA overlay",

abstract = "Coarse-grained FPGA overlays improve design productivity through software-like programmability and fast compilation. However, the effectiveness of overlays as accelerators is dependent on suitable interface and programming integration into a typically processor-based computing system, an aspect which has often been neglected in evaluations of overlays. We explore the integration of a time-multiplexed FPGA overlay over a server-class PCI Express interface. We show how this integration can be optimised to maximise performance, and evaluate the area overhead. We also propose a user-friendly programming model for such an overlay accelerator system.",

author = "Xiangwei Li and Kizheppatt Vipin and Maskell, {Douglas L.} and Fahmy, {Suhaib A.} and Jain, {Abhishek Kumar}",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE; 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020 ; Conference date: 10-10-2020 Through 21-10-2020",

year = "2020",

language = "English (US)",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings",

address = "United States",

}

Li, X, Vipin, K, Maskell, DL, Fahmy, SA & Jain, AK 2020, High throughput accelerator interface framework for a linear time-multiplexed FPGA overlay. in 2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings., 9181072, Proceedings - IEEE International Symposium on Circuits and Systems, vol. 2020-October, Institute of Electrical and Electronics Engineers Inc., 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020, Virtual, Online, 10/10/20.

High throughput accelerator interface framework for a linear time-multiplexed FPGA overlay. / Li, Xiangwei; Vipin, Kizheppatt; Maskell, Douglas L. et al.
2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2020. 9181072 (Proceedings - IEEE International Symposium on Circuits and Systems; Vol. 2020-October).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - High throughput accelerator interface framework for a linear time-multiplexed FPGA overlay

AU - Li, Xiangwei

AU - Vipin, Kizheppatt

AU - Maskell, Douglas L.

AU - Fahmy, Suhaib A.

AU - Jain, Abhishek Kumar

PY - 2020

Y1 - 2020

N2 - Coarse-grained FPGA overlays improve design productivity through software-like programmability and fast compilation. However, the effectiveness of overlays as accelerators is dependent on suitable interface and programming integration into a typically processor-based computing system, an aspect which has often been neglected in evaluations of overlays. We explore the integration of a time-multiplexed FPGA overlay over a server-class PCI Express interface. We show how this integration can be optimised to maximise performance, and evaluate the area overhead. We also propose a user-friendly programming model for such an overlay accelerator system.

AB - Coarse-grained FPGA overlays improve design productivity through software-like programmability and fast compilation. However, the effectiveness of overlays as accelerators is dependent on suitable interface and programming integration into a typically processor-based computing system, an aspect which has often been neglected in evaluations of overlays. We explore the integration of a time-multiplexed FPGA overlay over a server-class PCI Express interface. We show how this integration can be optimised to maximise performance, and evaluate the area overhead. We also propose a user-friendly programming model for such an overlay accelerator system.

UR - http://www.scopus.com/inward/record.url?scp=85108991946&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:85108991946

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - 2020 IEEE International Symposium on Circuits and Systems, ISCAS 2020 - Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 52nd IEEE International Symposium on Circuits and Systems, ISCAS 2020

Y2 - 10 October 2020 through 21 October 2020

ER -

High throughput accelerator interface framework for a linear time-multiplexed FPGA overlay

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Bibliographical note

ASJC Scopus subject areas

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