High-Performance Vertical Gate-All-Around Silicon Nanowire FET With High-kappa/Metal Gate

Yujia Zhai; Leo Mathew; Rajesh Rao; Marylene Palard; Sonali Chopra; John G. Ekerdt; Leonard F. Register; Sanjay K. Banerjee

doi:10.1109/TED.2014.2353658

High-Performance Vertical Gate-All-Around Silicon Nanowire FET With High-kappa/Metal Gate

Yujia Zhai, Leo Mathew, Rajesh Rao, Marylene Palard, Sonali Chopra, John G. Ekerdt, Leonard F. Register, Sanjay K. Banerjee

Research output: Contribution to journal › Article › peer-review

22 Scopus citations

Abstract

We present a vertical gate-all-around Si nanowire (SiNW) metal-oxide-semiconductor field-effect transistor with high-κ dielectric and TiN metal gate. The process flow is fully compatible with CMOS technologies. SiNWs are fabricated by deep Si reactive ion etching, gate-stack is formed by atomic layer deposition, and metal salicide is utilized as drain contact. The fabricated p-type gate-all-around SiNW metal-oxide-semiconductor field-effect transistors that have a gate length of 320 nm exhibit excellent characteristics with ION/IOFF > 104, subthreshold slope of 87 mV/decade, and 25 mV/V of drain-induced barrier lowering. Low-temperature characteristics are also presented. The demonstrated devices have potential applications in novel low-power logic circuits and as selection transistors for 4F2 cross-point memory cells.

Original language	English (US)
Pages (from-to)	3896-3900
Number of pages	5
Journal	IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume	61
Issue number	11
DOIs	https://doi.org/10.1109/TED.2014.2353658
State	Published - 2014
Externally published	Yes

Bibliographical note

KAUST Repository Item: Exported on 2021-10-08
Acknowledgements: This work was supported in part by the King Abdullah University of Science and Technology, Thuwal, Saudi Arabia, in part by the National Science Foundation, Nanosystems Engineering Research Center, through the Nanomanufacturing Systems for Mobile Computing and Mobile Energy Technologies, and in part by the National Nanotechnology Infrastructure Network Programs. The review of this brief was arranged by Editor W. Tsai.
This publication acknowledges KAUST support, but has no KAUST affiliated authors.

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10.1109/TED.2014.2353658

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@article{f93bb7e0599a4cfb93c030bc9a7a55c8,

title = "High-Performance Vertical Gate-All-Around Silicon Nanowire FET With High-kappa/Metal Gate",

abstract = "We present a vertical gate-all-around Si nanowire (SiNW) metal-oxide-semiconductor field-effect transistor with high-κ dielectric and TiN metal gate. The process flow is fully compatible with CMOS technologies. SiNWs are fabricated by deep Si reactive ion etching, gate-stack is formed by atomic layer deposition, and metal salicide is utilized as drain contact. The fabricated p-type gate-all-around SiNW metal-oxide-semiconductor field-effect transistors that have a gate length of 320 nm exhibit excellent characteristics with ION/IOFF > 104, subthreshold slope of 87 mV/decade, and 25 mV/V of drain-induced barrier lowering. Low-temperature characteristics are also presented. The demonstrated devices have potential applications in novel low-power logic circuits and as selection transistors for 4F2 cross-point memory cells.",

author = "Yujia Zhai and Leo Mathew and Rajesh Rao and Marylene Palard and Sonali Chopra and Ekerdt, {John G.} and Register, {Leonard F.} and Banerjee, {Sanjay K.}",

note = "KAUST Repository Item: Exported on 2021-10-08 Acknowledgements: This work was supported in part by the King Abdullah University of Science and Technology, Thuwal, Saudi Arabia, in part by the National Science Foundation, Nanosystems Engineering Research Center, through the Nanomanufacturing Systems for Mobile Computing and Mobile Energy Technologies, and in part by the National Nanotechnology Infrastructure Network Programs. The review of this brief was arranged by Editor W. Tsai. This publication acknowledges KAUST support, but has no KAUST affiliated authors.",

year = "2014",

doi = "10.1109/TED.2014.2353658",

language = "English (US)",

volume = "61",

pages = "3896--3900",

journal = "IEEE TRANSACTIONS ON ELECTRON DEVICES",

issn = "1557-9646",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "11",

}

TY - JOUR

T1 - High-Performance Vertical Gate-All-Around Silicon Nanowire FET With High-kappa/Metal Gate

AU - Zhai, Yujia

AU - Mathew, Leo

AU - Rao, Rajesh

AU - Palard, Marylene

AU - Chopra, Sonali

AU - Ekerdt, John G.

AU - Register, Leonard F.

AU - Banerjee, Sanjay K.

N1 - KAUST Repository Item: Exported on 2021-10-08 Acknowledgements: This work was supported in part by the King Abdullah University of Science and Technology, Thuwal, Saudi Arabia, in part by the National Science Foundation, Nanosystems Engineering Research Center, through the Nanomanufacturing Systems for Mobile Computing and Mobile Energy Technologies, and in part by the National Nanotechnology Infrastructure Network Programs. The review of this brief was arranged by Editor W. Tsai. This publication acknowledges KAUST support, but has no KAUST affiliated authors.

PY - 2014

Y1 - 2014

N2 - We present a vertical gate-all-around Si nanowire (SiNW) metal-oxide-semiconductor field-effect transistor with high-κ dielectric and TiN metal gate. The process flow is fully compatible with CMOS technologies. SiNWs are fabricated by deep Si reactive ion etching, gate-stack is formed by atomic layer deposition, and metal salicide is utilized as drain contact. The fabricated p-type gate-all-around SiNW metal-oxide-semiconductor field-effect transistors that have a gate length of 320 nm exhibit excellent characteristics with ION/IOFF > 104, subthreshold slope of 87 mV/decade, and 25 mV/V of drain-induced barrier lowering. Low-temperature characteristics are also presented. The demonstrated devices have potential applications in novel low-power logic circuits and as selection transistors for 4F2 cross-point memory cells.

AB - We present a vertical gate-all-around Si nanowire (SiNW) metal-oxide-semiconductor field-effect transistor with high-κ dielectric and TiN metal gate. The process flow is fully compatible with CMOS technologies. SiNWs are fabricated by deep Si reactive ion etching, gate-stack is formed by atomic layer deposition, and metal salicide is utilized as drain contact. The fabricated p-type gate-all-around SiNW metal-oxide-semiconductor field-effect transistors that have a gate length of 320 nm exhibit excellent characteristics with ION/IOFF > 104, subthreshold slope of 87 mV/decade, and 25 mV/V of drain-induced barrier lowering. Low-temperature characteristics are also presented. The demonstrated devices have potential applications in novel low-power logic circuits and as selection transistors for 4F2 cross-point memory cells.

UR - http://hdl.handle.net/10754/672254

UR - http://ieeexplore.ieee.org/document/6902756/

UR - http://www.scopus.com/inward/record.url?scp=84908553191&partnerID=8YFLogxK

U2 - 10.1109/TED.2014.2353658

DO - 10.1109/TED.2014.2353658

M3 - Article

SN - 1557-9646

VL - 61

SP - 3896

EP - 3900

JO - IEEE TRANSACTIONS ON ELECTRON DEVICES

JF - IEEE TRANSACTIONS ON ELECTRON DEVICES

IS - 11

ER -

High-Performance Vertical Gate-All-Around Silicon Nanowire FET With High-kappa/Metal Gate

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