TY - GEN
T1 - High Order FIR Filter Hardware Implementation Complexity Reduction
AU - Degtyarev, Alexander
AU - Saifullin, Karim
AU - Bakhurin, Sergey
N1 - KAUST Repository Item: Exported on 2022-09-14
PY - 2022/6/13
Y1 - 2022/6/13
N2 - In this paper, the authors propose an algorithm for the hardware implementation complexity reduction of high order FIR-filters. Current algorithm reduces FIR-filters' a number of multipliers expressing initial impulse response samples through the other initial impulse response samples. This approach allows replacing multipliers with shift registers and adders, which leads to reduction of FIR-filters' power consumption and required crystal area. Algorithm works with all types of filters: Low Pass, High Pass, Band Pass, Band Stop and also it supports FIR-filters with symmetrical and asymmetrical impulse responses.
AB - In this paper, the authors propose an algorithm for the hardware implementation complexity reduction of high order FIR-filters. Current algorithm reduces FIR-filters' a number of multipliers expressing initial impulse response samples through the other initial impulse response samples. This approach allows replacing multipliers with shift registers and adders, which leads to reduction of FIR-filters' power consumption and required crystal area. Algorithm works with all types of filters: Low Pass, High Pass, Band Pass, Band Stop and also it supports FIR-filters with symmetrical and asymmetrical impulse responses.
UR - http://hdl.handle.net/10754/679014
UR - https://ieeexplore.ieee.org/document/9790772/
UR - http://www.scopus.com/inward/record.url?scp=85133449951&partnerID=8YFLogxK
U2 - 10.1109/DSPA53304.2022.9790772
DO - 10.1109/DSPA53304.2022.9790772
M3 - Conference contribution
SN - 978-1-6654-9444-1
BT - 2022 24th International Conference on Digital Signal Processing and its Applications (DSPA)
PB - IEEE
ER -