The scaling of silicon metal–oxide–semiconductor field-effect transistors has followed Moore’s law for decades, but the physical thinning of silicon at sub-ten-nanometre technology nodes introduces issues such as leakage currents1. Two-dimensional (2D) layered semiconductors, with an atomic thickness that allows superior gate-field penetration, are of interest as channel materials for future transistors2,3. However, the integration of high-dielectric-constant (κ) materials with 2D materials, while scaling their capacitance equivalent thickness (CET), has proved challenging. Here we explore transferrable ultrahigh-κ single-crystalline perovskite strontium-titanium-oxide membranes as a gate dielectric for 2D field-effect transistors. Our perovskite membranes exhibit a desirable sub-one-nanometre CET with a low leakage current (less than 10−2 amperes per square centimetre at 2.5 megavolts per centimetre). We find that the van der Waals gap between strontium-titanium-oxide dielectrics and 2D semiconductors mitigates the unfavourable fringing-induced barrier-lowering effect resulting from the use of ultrahigh-κ dielectrics4. Typical short-channel transistors made of scalable molybdenum-disulfide films by chemical vapour deposition and strontium-titanium-oxide dielectrics exhibit steep subthreshold swings down to about 70 millivolts per decade and on/off current ratios up to 107, which matches the low-power specifications suggested by the latest International Roadmap for Devices and Systems5.