TY - GEN
T1 - Heterogeneous memory management for 3D-DRAM and external DRAM with QoS
AU - Tran, Le Nguyen
AU - Kurdahi, Fadi J.
AU - Eltawil, Ahmed M.
AU - Homayoun, Houman
N1 - Generated from Scopus record by KAUST IRTS on 2019-11-20
PY - 2013/5/20
Y1 - 2013/5/20
N2 - This paper presents an innovative memory management approach to utilize both 3D-DRAM and external DRAM (ex-DRAM). Our approach dynamically allocates and relocates memory blocks between the 3D-DRAM and the ex-DRAM to exploit the high memory bandwidth and the low memory latency of the 3D-DRAM as well as the high capacity and the low cost of the ex-DRAM. Our simulation shows that in workloads that are not memory intensive, our memory management technique transfers all active memory blocks to the 3D-DRAM which runs faster than the ex-DRAM. In memory intensive workloads, our memory management technique utilizes both the 3D-DRAM and the ex-DRAM to increase the memory bandwidth to alleviate bandwidth congestion. Our approach supports Quality of Service (QoS) for 'latency sensitive', 'bandwidth sensitive', and 'insensitive' applications. To improve the performance and satisfy a certain level of QoS, memory blocks of different application types are allocated differently. Compared to the scratchpad memory management mechanism, the average memory access latency of our approach decreases by 19% and 23%, while performance improves by up to 5% and 12% in single threaded benchmarks and multi-threaded benchmarks respectively. Moreover, using our approach, applications do not need to manage memory explicitly like in the scratchpad case. Our memory block relocation comes with negligible performance overhead, particularly for applications which have high spatial memory locality. © 2013 IEEE.
AB - This paper presents an innovative memory management approach to utilize both 3D-DRAM and external DRAM (ex-DRAM). Our approach dynamically allocates and relocates memory blocks between the 3D-DRAM and the ex-DRAM to exploit the high memory bandwidth and the low memory latency of the 3D-DRAM as well as the high capacity and the low cost of the ex-DRAM. Our simulation shows that in workloads that are not memory intensive, our memory management technique transfers all active memory blocks to the 3D-DRAM which runs faster than the ex-DRAM. In memory intensive workloads, our memory management technique utilizes both the 3D-DRAM and the ex-DRAM to increase the memory bandwidth to alleviate bandwidth congestion. Our approach supports Quality of Service (QoS) for 'latency sensitive', 'bandwidth sensitive', and 'insensitive' applications. To improve the performance and satisfy a certain level of QoS, memory blocks of different application types are allocated differently. Compared to the scratchpad memory management mechanism, the average memory access latency of our approach decreases by 19% and 23%, while performance improves by up to 5% and 12% in single threaded benchmarks and multi-threaded benchmarks respectively. Moreover, using our approach, applications do not need to manage memory explicitly like in the scratchpad case. Our memory block relocation comes with negligible performance overhead, particularly for applications which have high spatial memory locality. © 2013 IEEE.
UR - http://ieeexplore.ieee.org/document/6509676/
UR - http://www.scopus.com/inward/record.url?scp=84877775456&partnerID=8YFLogxK
U2 - 10.1109/ASPDAC.2013.6509676
DO - 10.1109/ASPDAC.2013.6509676
M3 - Conference contribution
SN - 9781467330299
BT - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
ER -