Gate first high-k/metal gate stacks with zero SiOx interface achieving EOT=0.59nm for 16nm application

J. Huang; D. Heh; P. Sivasubramani; P. D. Kirsch; G. Bersuker; D. C. Gilmer; M. A. Quevedo-Lopez; M. M. Hussain; P. Majhi; P. Lysaght; H. Park; N. Goel; C. Young; C. S. Park; C. Park; M. Cruz; V. Diaz; P. Y. Hung; J. Price; H. H. Tseng; R. Jammy

Gate first high-k/metal gate stacks with zero SiO_x interface achieving EOT=0.59nm for 16nm application

J. Huang^*, D. Heh, P. Sivasubramani, P. D. Kirsch, G. Bersuker, D. C. Gilmer, M. A. Quevedo-Lopez, M. M. Hussain, P. Majhi, P. Lysaght, H. Park, N. Goel, C. Young, C. S. Park, C. Park, M. Cruz, V. Diaz, P. Y. Hung, J. Price, H. H. TsengR. Jammy

^*Corresponding author for this work

Computer, Electrical and Mathematical Sciences and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

52 Scopus citations

Abstract

Gate first 0.59nm EOT HfO_x/metal gate stacks for 16 nm node application are demonstrated for the first time. By controlling O during HfO_x deposition, "zero" low-k SiO_x interface (ZIL) forms despite a 1020oC activation anneal. This 0.59nm EOT is a 30% improvement over a state of the art 32nm HK/MG technology [1]. We compare and demonstrate for the first time the improved scalability of ZIL HfO_x vs. exotic higher-k. Transistors made with ZIL HfO_x show good interfaces (SS=70-80 mV/dec, N_it=5×10¹⁰/cm ²) and performance (10% I_on-I_off boost vs. EOT=0.95nm), despite mobility loss. Factors contributing to mobility loss in ZIL HfO_x are discussed.

Original language	English (US)
Title of host publication	2009 Symposium on VLSI Technology, VLSIT 2009
Pages	34-35
Number of pages	2
State	Published - 2009
Event	2009 Symposium on VLSI Technology, VLSIT 2009 - Kyoto, Japan Duration: Jun 16 2009 → Jun 18 2009

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)	0743-1562

Other

Other	2009 Symposium on VLSI Technology, VLSIT 2009
Country/Territory	Japan
City	Kyoto
Period	06/16/09 → 06/18/09

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

Huang, J., Heh, D., Sivasubramani, P., Kirsch, P. D., Bersuker, G., Gilmer, D. C., Quevedo-Lopez, M. A., Hussain, M. M., Majhi, P., Lysaght, P., Park, H., Goel, N., Young, C., Park, C. S., Park, C., Cruz, M., Diaz, V., Hung, P. Y., Price, J., ... Jammy, R. (2009). Gate first high-k/metal gate stacks with zero SiO_x interface achieving EOT=0.59nm for 16nm application. In 2009 Symposium on VLSI Technology, VLSIT 2009 (pp. 34-35). Article 5200624 (Digest of Technical Papers - Symposium on VLSI Technology).

@inproceedings{c69b6e92814a49b6a72125a048dd6271,

title = "Gate first high-k/metal gate stacks with zero SiOx interface achieving EOT=0.59nm for 16nm application",

abstract = "Gate first 0.59nm EOT HfOx/metal gate stacks for 16 nm node application are demonstrated for the first time. By controlling O during HfOx deposition, {"}zero{"} low-k SiOx interface (ZIL) forms despite a 1020oC activation anneal. This 0.59nm EOT is a 30% improvement over a state of the art 32nm HK/MG technology [1]. We compare and demonstrate for the first time the improved scalability of ZIL HfOx vs. exotic higher-k. Transistors made with ZIL HfOx show good interfaces (SS=70-80 mV/dec, Nit=5×1010/cm 2) and performance (10% Ion-Ioff boost vs. EOT=0.95nm), despite mobility loss. Factors contributing to mobility loss in ZIL HfOx are discussed.",

author = "J. Huang and D. Heh and P. Sivasubramani and Kirsch, {P. D.} and G. Bersuker and Gilmer, {D. C.} and Quevedo-Lopez, {M. A.} and Hussain, {M. M.} and P. Majhi and P. Lysaght and H. Park and N. Goel and C. Young and Park, {C. S.} and C. Park and M. Cruz and V. Diaz and Hung, {P. Y.} and J. Price and Tseng, {H. H.} and R. Jammy",

year = "2009",

language = "English (US)",

isbn = "9784863480094",

series = "Digest of Technical Papers - Symposium on VLSI Technology",

pages = "34--35",

booktitle = "2009 Symposium on VLSI Technology, VLSIT 2009",

note = "2009 Symposium on VLSI Technology, VLSIT 2009 ; Conference date: 16-06-2009 Through 18-06-2009",

}

Huang, J, Heh, D, Sivasubramani, P, Kirsch, PD, Bersuker, G, Gilmer, DC, Quevedo-Lopez, MA, Hussain, MM, Majhi, P, Lysaght, P, Park, H, Goel, N, Young, C, Park, CS, Park, C, Cruz, M, Diaz, V, Hung, PY, Price, J, Tseng, HH & Jammy, R 2009, Gate first high-k/metal gate stacks with zero SiO_x interface achieving EOT=0.59nm for 16nm application. in 2009 Symposium on VLSI Technology, VLSIT 2009., 5200624, Digest of Technical Papers - Symposium on VLSI Technology, pp. 34-35, 2009 Symposium on VLSI Technology, VLSIT 2009, Kyoto, Japan, 06/16/09.

Gate first high-k/metal gate stacks with zero SiO_x interface achieving EOT=0.59nm for 16nm application. / Huang, J.; Heh, D.; Sivasubramani, P. et al.
2009 Symposium on VLSI Technology, VLSIT 2009. 2009. p. 34-35 5200624 (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Gate first high-k/metal gate stacks with zero SiOx interface achieving EOT=0.59nm for 16nm application

AU - Huang, J.

AU - Heh, D.

AU - Sivasubramani, P.

AU - Kirsch, P. D.

AU - Bersuker, G.

AU - Gilmer, D. C.

AU - Quevedo-Lopez, M. A.

AU - Hussain, M. M.

AU - Majhi, P.

AU - Lysaght, P.

AU - Park, H.

AU - Goel, N.

AU - Young, C.

AU - Park, C. S.

AU - Park, C.

AU - Cruz, M.

AU - Diaz, V.

AU - Hung, P. Y.

AU - Price, J.

AU - Tseng, H. H.

AU - Jammy, R.

PY - 2009

Y1 - 2009

N2 - Gate first 0.59nm EOT HfOx/metal gate stacks for 16 nm node application are demonstrated for the first time. By controlling O during HfOx deposition, "zero" low-k SiOx interface (ZIL) forms despite a 1020oC activation anneal. This 0.59nm EOT is a 30% improvement over a state of the art 32nm HK/MG technology [1]. We compare and demonstrate for the first time the improved scalability of ZIL HfOx vs. exotic higher-k. Transistors made with ZIL HfOx show good interfaces (SS=70-80 mV/dec, Nit=5×1010/cm 2) and performance (10% Ion-Ioff boost vs. EOT=0.95nm), despite mobility loss. Factors contributing to mobility loss in ZIL HfOx are discussed.

AB - Gate first 0.59nm EOT HfOx/metal gate stacks for 16 nm node application are demonstrated for the first time. By controlling O during HfOx deposition, "zero" low-k SiOx interface (ZIL) forms despite a 1020oC activation anneal. This 0.59nm EOT is a 30% improvement over a state of the art 32nm HK/MG technology [1]. We compare and demonstrate for the first time the improved scalability of ZIL HfOx vs. exotic higher-k. Transistors made with ZIL HfOx show good interfaces (SS=70-80 mV/dec, Nit=5×1010/cm 2) and performance (10% Ion-Ioff boost vs. EOT=0.95nm), despite mobility loss. Factors contributing to mobility loss in ZIL HfOx are discussed.

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M3 - Conference contribution

AN - SCOPUS:71049153326

SN - 9784863480094

T3 - Digest of Technical Papers - Symposium on VLSI Technology

SP - 34

EP - 35

BT - 2009 Symposium on VLSI Technology, VLSIT 2009

T2 - 2009 Symposium on VLSI Technology, VLSIT 2009

Y2 - 16 June 2009 through 18 June 2009

ER -