TY - PAT
T1 - Fully Digital Chaotic Differential Equation-based Systems And Methods
AU - Radwan, Ahmed G.
AU - Zidan, Mohammed A.
AU - Salama, Khaled N.
N1 - KAUST Repository Item: Exported on 2019-02-13
PY - 2012/9/6
Y1 - 2012/9/6
N2 - Various embodiments are provided for fully digital chaotic differential equation-based systems and methods. In one embodiment, among others, a digital circuit includes digital state registers and one or more digital logic modules configured to obtain a first value from two or more of the digital state registers; determine a second value based upon the obtained first values and a chaotic differential equation; and provide the second value to set a state of one of the plurality of digital state registers. In another embodiment, a digital circuit includes digital state registers, digital logic modules configured to obtain outputs from a subset of the digital shift registers and to provide the input based upon a chaotic differential equation for setting a state of at least one of the subset of digital shift registers, and a digital clock configured to provide a clock signal for operating the digital shift registers.
AB - Various embodiments are provided for fully digital chaotic differential equation-based systems and methods. In one embodiment, among others, a digital circuit includes digital state registers and one or more digital logic modules configured to obtain a first value from two or more of the digital state registers; determine a second value based upon the obtained first values and a chaotic differential equation; and provide the second value to set a state of one of the plurality of digital state registers. In another embodiment, a digital circuit includes digital state registers, digital logic modules configured to obtain outputs from a subset of the digital shift registers and to provide the input based upon a chaotic differential equation for setting a state of at least one of the subset of digital shift registers, and a digital clock configured to provide a clock signal for operating the digital shift registers.
UR - http://hdl.handle.net/10754/595069
UR - http://appft.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PG01&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.html&r=1&f=G&l=50&s1=%2220120226724%22.PGNR.&OS=DN/20120226724&RS=DN/20120226724
UR - http://assignment.uspto.gov/#/search?adv=publNum:20120226724
UR - http://www.google.com/patents/US20120226724
UR - http://worldwide.espacenet.com/publicationDetails/biblio?CC=US&NR=2012226724A1&KC=A1&FT=D
M3 - Patent
M1 - US9600238B2
ER -