TY - GEN
T1 - Fibonacci-based hardware post-processing for non-autonomous signum hyperchaotic system
AU - Mansingka, Abhinav S.
AU - Barakat, Mohamed L.
AU - Zidan, Mohammed A.
AU - Radwan, Ahmed Gomaa
AU - Salama, Khaled N.
N1 - KAUST Repository Item: Exported on 2020-10-01
PY - 2013/12
Y1 - 2013/12
N2 - This paper presents a hardware implementation of a robust non-autonomous hyperchaotic-based PRNG driven by a 256-bit LFSR. The original chaotic output is post-processed using a novel technique based on the Fibonacci series, bitwise XOR, rotation, and feedback. The proposed post-processing technique preserves the throughput of the system and enhances the randomness in the output which is verified by successfully passing all NIST SP. 800-22 tests. The system is realized on a Xilinx Virtex 4 FPGA achieving throughput up to 13.165 Gbits/s for 16-bit bus-width surpassing previously reported CB-PRNGs. © 2013 IEEE.
AB - This paper presents a hardware implementation of a robust non-autonomous hyperchaotic-based PRNG driven by a 256-bit LFSR. The original chaotic output is post-processed using a novel technique based on the Fibonacci series, bitwise XOR, rotation, and feedback. The proposed post-processing technique preserves the throughput of the system and enhances the randomness in the output which is verified by successfully passing all NIST SP. 800-22 tests. The system is realized on a Xilinx Virtex 4 FPGA achieving throughput up to 13.165 Gbits/s for 16-bit bus-width surpassing previously reported CB-PRNGs. © 2013 IEEE.
UR - http://hdl.handle.net/10754/564830
UR - http://ieeexplore.ieee.org/document/6717834/
UR - http://www.scopus.com/inward/record.url?scp=84894207761&partnerID=8YFLogxK
U2 - 10.1109/ICITCS.2013.6717834
DO - 10.1109/ICITCS.2013.6717834
M3 - Conference contribution
SN - 9781479928453
BT - 2013 International Conference on IT Convergence and Security (ICITCS)
PB - Institute of Electrical and Electronics Engineers (IEEE)
ER -