Fast error aware model for arithmetic and logic circuits

Samy Zaynoun, Muhammad S. Khairy, Ahmed M. Eltawil, Fadi J. Kurdahi, Amin Khajeh

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Scopus citations


As a result of supply voltage reduction and process variations effects, the error free margin for dynamic voltage scaling has been drastically reduced. This paper presents an error aware model for arithmetic and logic circuits that accurately and rapidly estimates the propagation delays of the output bits in a digital block operating under voltage scaling to identify circuit-level failures (timing violations) within the block. Consequently, these failure models are then used to examine how circuit-level failures affect system-level reliability. A case study consisting of a CORDIC DSP unit employing the proposed model provides tradeoffs between power, performance and reliability. © 2012 IEEE.
Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
StatePublished - Dec 1 2012
Externally publishedYes

Bibliographical note

Generated from Scopus record by KAUST IRTS on 2019-11-20


Dive into the research topics of 'Fast error aware model for arithmetic and logic circuits'. Together they form a unique fingerprint.

Cite this