Fabrication of 0.15 im SOI p-MOSFKTs using synchrotron radiation X-ray lithography

15 μm SOI p-MOSFFTs were fabricated hv XRL (x-ray lithography) for gate and contact layer's patterning and optical lithograph) for other layers*. We prepared x-ray mask blank with 2 μm in thick silicon nitride film as a membrane as shown in Fig. 1. The additive process" was utilized for x-ray mask fabrication as indicated in Fig. 2. We deposited 10 nm thick chromium layer and 200 nm thick gold layer over the membrane for the effective absorber electroplating. 400 nm thick gold film was electroplated as an absorber after the patterning by electron-beam lithography using resist FMMA. For the XRL process, Alladin storage ring of 800 MeV energy in Wisconsin University in U.S.A. and Karl Suss XRS 200 stepper were utilized. We used SAL 603 negative resist(from Shipley Co.) and AZ-PF positive resist(from Hoechst Co.) of 0.75 μm thickness for the patterning of gate poly-Si and contact hole, respectively. The gap distance between mask and wafer on the stepper was set at 40 μm in automatic mode and the irradiation dose was 200 mJ/cm² The alignment accuracy, die by die, was better than 150 nm. Figure 3 shows the vernier patterns which indicate the good alignment and XRL patterning results for poly-Si layer of 0.15 μin line and space. SOI p-channel MOSFHTs were fabricated by a conventional CMOS process except two XRL steps for the gate and contact layers on SIMOX SOI substrates. 6.5 nm gate oxide was thermally grown in dry O₂, ambient at 900 °C. The final surface silicon thickness was about 0.1 μm, while the thickness of the source/drain region was 0.03 m thinner than that of the channel region. Figure 4(a) shows the TFM photograph of the fabricated SOI p-MOSFRT and figure 4(b) shows the I V characteristics of the device. As shown in the l-V characteristics, the saturation drain current ld.M was about J (K) jjA/fjm and the threshold voltage V₁, was about 0.4 V. The breakdown voltage BV, s between the source and drain measured at V_a. = 0 V and I₄ = 10 nA was larger than 4 V. The lower I, i( was caused mainly due to the high source/drain resistance resulted from the non-silicided thin Si layers. We also measured the interface trap density I):. by using the charge pumping current method to confirm any damage at the Si/SiO₂: interface of the p-MOSFFT on the normal bulk-Si substrate. Measured Dit was about 4 x 10 eV cm . This value is almost same as that of previous measurement1 1 and somewhat lager than than the value of 1.5 x 10 ^thcm² which was measured in the device fabricated using conventional optical lithography.