Enhanced performance and SRAM stability in FinFET with reduced process steps for source/drain doping

J. W. Yang; H. R. Harris; M. M. Hussain; B. Sassman; H. H. Tseng; R. Jammy

doi:10.1109/VTSA.2008.4530779

Enhanced performance and SRAM stability in FinFET with reduced process steps for source/drain doping

J. W. Yang^*, H. R. Harris, M. M. Hussain, B. Sassman, H. H. Tseng, R. Jammy

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

11 Scopus citations

Abstract

Improved static noise margin in SRAM of 18% and decreased intrinsic inverter delay of 6% is demonstrated for the first time in double-gate CMOS finFET with gate-source/drain underlap doping. The excellent results are achieved by optimization of the spacer while simplifying the processing of source/drain region by skipping costly implants. Improved circuit and device performance with reduced processing steps malee finFETs a more attractive option for 32nm technology node and beyond.

Original language	English (US)
Title of host publication	2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA
Pages	20-21
Number of pages	2
DOIs	https://doi.org/10.1109/VTSA.2008.4530779
State	Published - 2008
Externally published	Yes
Event	2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA - Hsinchu, Taiwan, Province of China Duration: Apr 21 2008 → Apr 23 2008

Other

Other	2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA
Country/Territory	Taiwan, Province of China
City	Hsinchu
Period	04/21/08 → 04/23/08

ASJC Scopus subject areas

Engineering(all)

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10.1109/VTSA.2008.4530779

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title = "Enhanced performance and SRAM stability in FinFET with reduced process steps for source/drain doping",

abstract = "Improved static noise margin in SRAM of 18% and decreased intrinsic inverter delay of 6% is demonstrated for the first time in double-gate CMOS finFET with gate-source/drain underlap doping. The excellent results are achieved by optimization of the spacer while simplifying the processing of source/drain region by skipping costly implants. Improved circuit and device performance with reduced processing steps malee finFETs a more attractive option for 32nm technology node and beyond.",

author = "Yang, {J. W.} and Harris, {H. R.} and Hussain, {M. M.} and B. Sassman and Tseng, {H. H.} and R. Jammy",

year = "2008",

doi = "10.1109/VTSA.2008.4530779",

language = "English (US)",

isbn = "9781424416158",

pages = "20--21",

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note = "2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA ; Conference date: 21-04-2008 Through 23-04-2008",

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Yang, JW, Harris, HR, Hussain, MM, Sassman, B, Tseng, HH & Jammy, R 2008, Enhanced performance and SRAM stability in FinFET with reduced process steps for source/drain doping. in 2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA., 4530779, pp. 20-21, 2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA, Hsinchu, Taiwan, Province of China, 04/21/08. https://doi.org/10.1109/VTSA.2008.4530779

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AU - Harris, H. R.

AU - Hussain, M. M.

AU - Sassman, B.

AU - Tseng, H. H.

AU - Jammy, R.

PY - 2008

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AB - Improved static noise margin in SRAM of 18% and decreased intrinsic inverter delay of 6% is demonstrated for the first time in double-gate CMOS finFET with gate-source/drain underlap doping. The excellent results are achieved by optimization of the spacer while simplifying the processing of source/drain region by skipping costly implants. Improved circuit and device performance with reduced processing steps malee finFETs a more attractive option for 32nm technology node and beyond.

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M3 - Conference contribution

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BT - 2008 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA

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Y2 - 21 April 2008 through 23 April 2008

ER -

Enhanced performance and SRAM stability in FinFET with reduced process steps for source/drain doping

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