Energy-Efficient Vertically Stacked NSFET-Based CTM for Logic in-Memory Computing

Md Hasan Raza Ansari; Naveen Kumar; Vihar Georgiev; Nazek El-Atab

doi:10.1109/NANO61778.2024.10628885

Energy-Efficient Vertically Stacked NSFET-Based CTM for Logic in-Memory Computing

Md Hasan Raza Ansari, Naveen Kumar, Vihar Georgiev, Nazek El-Atab^*

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

This work highlights the implementation of Boolean logic functions (AND, OR, NOR, XOR, and XNOR) in two steps for logic in-memory computing applications through a double gate vertically stacked nanosheet-based charge-trapping memory (DG-NSFET-CTM). The charge-trapping memory operation with high-κ blocking oxide material is based on the Fowler-Nordheim (FN) tunneling mechanism at a lower voltage (± 6V), which makes the device energy efficient. The device achieves a memory window of 1.77 V and consumes less energy (45.5 fJ) during inference. The work also shows the effect of vertically stacking nanosheets on the implementation of logic gates and energy consumption. The obtained results confirm the proposed dual gate NSFET-based CTM could be a promising candidate for next-generation in-memory computing.

Original language	English (US)
Title of host publication	2024 IEEE 24th International Conference on Nanotechnology, NANO 2024
Publisher	IEEE Computer Society
Pages	370-374
Number of pages	5
ISBN (Electronic)	9798350386240
DOIs	https://doi.org/10.1109/NANO61778.2024.10628885
State	Published - 2024
Event	24th IEEE International Conference on Nanotechnology, NANO 2024 - Gijon, Spain Duration: Jul 8 2024 → Jul 11 2024

Publication series

Name	Proceedings of the IEEE Conference on Nanotechnology
ISSN (Print)	1944-9399
ISSN (Electronic)	1944-9380

Conference

Conference	24th IEEE International Conference on Nanotechnology, NANO 2024
Country/Territory	Spain
City	Gijon
Period	07/8/24 → 07/11/24

Bibliographical note

Publisher Copyright:
© 2024 IEEE.

Keywords

Boolean logic functions
Charge-trapping Memory
energy-efficient and high density
in-memory computing
Nanosheet FET

ASJC Scopus subject areas

Bioengineering
Electrical and Electronic Engineering
Materials Chemistry
Condensed Matter Physics

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/NANO61778.2024.10628885

Cite this

@inproceedings{78d06e09890246ff9f6fddad313b42f4,

title = "Energy-Efficient Vertically Stacked NSFET-Based CTM for Logic in-Memory Computing",

abstract = "This work highlights the implementation of Boolean logic functions (AND, OR, NOR, XOR, and XNOR) in two steps for logic in-memory computing applications through a double gate vertically stacked nanosheet-based charge-trapping memory (DG-NSFET-CTM). The charge-trapping memory operation with high-κ blocking oxide material is based on the Fowler-Nordheim (FN) tunneling mechanism at a lower voltage (± 6V), which makes the device energy efficient. The device achieves a memory window of 1.77 V and consumes less energy (45.5 fJ) during inference. The work also shows the effect of vertically stacking nanosheets on the implementation of logic gates and energy consumption. The obtained results confirm the proposed dual gate NSFET-based CTM could be a promising candidate for next-generation in-memory computing.",

keywords = "Boolean logic functions, Charge-trapping Memory, energy-efficient and high density, in-memory computing, Nanosheet FET",

author = "\{Raza Ansari\}, \{Md Hasan\} and Naveen Kumar and Vihar Georgiev and Nazek El-Atab",

note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 24th IEEE International Conference on Nanotechnology, NANO 2024 ; Conference date: 08-07-2024 Through 11-07-2024",

year = "2024",

doi = "10.1109/NANO61778.2024.10628885",

language = "English (US)",

series = "Proceedings of the IEEE Conference on Nanotechnology",

publisher = "IEEE Computer Society",

pages = "370--374",

booktitle = "2024 IEEE 24th International Conference on Nanotechnology, NANO 2024",

address = "United States",

}

Raza Ansari, MH, Kumar, N, Georgiev, V & El-Atab, N 2024, Energy-Efficient Vertically Stacked NSFET-Based CTM for Logic in-Memory Computing. in 2024 IEEE 24th International Conference on Nanotechnology, NANO 2024. Proceedings of the IEEE Conference on Nanotechnology, IEEE Computer Society, pp. 370-374, 24th IEEE International Conference on Nanotechnology, NANO 2024, Gijon, Spain, 07/8/24. https://doi.org/10.1109/NANO61778.2024.10628885

Energy-Efficient Vertically Stacked NSFET-Based CTM for Logic in-Memory Computing. / Raza Ansari, Md Hasan; Kumar, Naveen; Georgiev, Vihar et al.
2024 IEEE 24th International Conference on Nanotechnology, NANO 2024. IEEE Computer Society, 2024. p. 370-374 (Proceedings of the IEEE Conference on Nanotechnology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Energy-Efficient Vertically Stacked NSFET-Based CTM for Logic in-Memory Computing

AU - Raza Ansari, Md Hasan

AU - Kumar, Naveen

AU - Georgiev, Vihar

AU - El-Atab, Nazek

PY - 2024

Y1 - 2024

N2 - This work highlights the implementation of Boolean logic functions (AND, OR, NOR, XOR, and XNOR) in two steps for logic in-memory computing applications through a double gate vertically stacked nanosheet-based charge-trapping memory (DG-NSFET-CTM). The charge-trapping memory operation with high-κ blocking oxide material is based on the Fowler-Nordheim (FN) tunneling mechanism at a lower voltage (± 6V), which makes the device energy efficient. The device achieves a memory window of 1.77 V and consumes less energy (45.5 fJ) during inference. The work also shows the effect of vertically stacking nanosheets on the implementation of logic gates and energy consumption. The obtained results confirm the proposed dual gate NSFET-based CTM could be a promising candidate for next-generation in-memory computing.

AB - This work highlights the implementation of Boolean logic functions (AND, OR, NOR, XOR, and XNOR) in two steps for logic in-memory computing applications through a double gate vertically stacked nanosheet-based charge-trapping memory (DG-NSFET-CTM). The charge-trapping memory operation with high-κ blocking oxide material is based on the Fowler-Nordheim (FN) tunneling mechanism at a lower voltage (± 6V), which makes the device energy efficient. The device achieves a memory window of 1.77 V and consumes less energy (45.5 fJ) during inference. The work also shows the effect of vertically stacking nanosheets on the implementation of logic gates and energy consumption. The obtained results confirm the proposed dual gate NSFET-based CTM could be a promising candidate for next-generation in-memory computing.

KW - Boolean logic functions

KW - Charge-trapping Memory

KW - energy-efficient and high density

KW - in-memory computing

KW - Nanosheet FET

UR - http://www.scopus.com/inward/record.url?scp=85203150891&partnerID=8YFLogxK

U2 - 10.1109/NANO61778.2024.10628885

DO - 10.1109/NANO61778.2024.10628885

M3 - Conference contribution

AN - SCOPUS:85203150891

T3 - Proceedings of the IEEE Conference on Nanotechnology

SP - 370

EP - 374

BT - 2024 IEEE 24th International Conference on Nanotechnology, NANO 2024

PB - IEEE Computer Society

T2 - 24th IEEE International Conference on Nanotechnology, NANO 2024

Y2 - 8 July 2024 through 11 July 2024

ER -

Energy-Efficient Vertically Stacked NSFET-Based CTM for Logic in-Memory Computing

Abstract

Publication series

Conference

Bibliographical note

Keywords

ASJC Scopus subject areas

UN SDGs

Access to Document

Other files and links

Fingerprint

Cite this