Dynamic voltage scaling continuous adaptive-size cell design technique

Sami Kirolos, Yehia Massoud

Research output: Contribution to journalArticlepeer-review

1 Scopus citations


In this paper, we present an adaptive circuit design that is capable of increasing the effective size-ratio of combinational logic gates to extend the balanced operation in the subthreshold region as well as to maintain high performance at the nominal VDD. We optimize the sizes of the PMOS transistors in the pull-up network for minimum power dissipation and propagation delay over a wide range of supply voltage. In addition to the minimized energy operation, the dynamically adjustable gate size-ratio allows the gate to preserve a symmetric voltage transfer characteristic at both normal supply and subthreshold operation, which translates to maximized noise margins. Simulation results show that up to 70.9% reduction in the energy can be achieved for a ring oscillator, as compared to the fixed size design capable of operating under supply voltage in the range of 75 mV to 1.2 V. For designs working under dynamic voltage scaling schemes, our technique presents a very effective and efficient solution for balanced minimum energy operation in the subthreshold region while preserving high performance at the nominal supply voltage. © 2008 World Scientific Publishing Company.
Original languageEnglish (US)
Pages (from-to)871-883
Number of pages13
JournalJournal of Circuits, Systems and Computers
Issue number5
StatePublished - Oct 1 2008
Externally publishedYes

Bibliographical note

Generated from Scopus record by KAUST IRTS on 2022-09-13

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering


Dive into the research topics of 'Dynamic voltage scaling continuous adaptive-size cell design technique'. Together they form a unique fingerprint.

Cite this