As process technology continues to scale into the nanoscale regime and overall system complexity increases, the reduced order modeling of on-chip interconnect plays a crucial role in characterizing VLSI system performance. In this paper, we develop a dynamic multi-point rational interpolation method based on Krylov subspace techniques to generate reduced order interconnect models that are accurate across a wide-range of frequencies. We dynamically select interpolation point by applying a cubic spline-based algorithm to detect complex regions in the system's frequency response. The results indicate that our method provides greater accuracy than techniques that apply multi-shift Krylov subspace methods with uniform interpolation points. © 2006 IEEE.
|Title of host publication
|2006 IEEE Dallas/CAS Workshop onDesign, Applications, Integration and Software, DCAS-06
|Number of pages
|Published - Dec 1 2006