Drain bias stress and memory effects in AlGaN/GaN heterostructure field-effect transistors with p-GaN gate

Takayuki Sugiyama, Yoshio Honda, Masahito Yamaguchi, Hiroshi Amano, Yoshinori Oshimura, Daisuke Iida, Motoaki Iwaya, Isamu Akasaki

Research output: Contribution to journalArticlepeer-review

Abstract

We measured the drain bias stress effects in normally off mode AlGaN/GaN (JHFETs) with a p-GaN gate, whose AlGaN barrier was exposed to air by dry etching. A large current collapse and a memory effect decreased the drain current (IDS). IDS of an unpassivated sample became the off leakage level of normally off mode JHFETs at a drain stress bias of 15 V. On the other hand, IDS in SiN-passivated JHFETs decreased at a slow rate upon applying drain stress bias. The decrease in IDS in SiN-passivated JHFETs was almost the same as that in as-grown HFETs. These drain stress and memory effects were perfectly deletable by light exposure, and were rewritable similarly in an EPROM. © 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.
Original languageEnglish (US)
Pages (from-to)2424-2426
Number of pages3
JournalPhysica Status Solidi (C) Current Topics in Solid State Physics
Volume8
Issue number7-8
DOIs
StatePublished - Jul 1 2011
Externally publishedYes

Bibliographical note

Generated from Scopus record by KAUST IRTS on 2023-09-21

ASJC Scopus subject areas

  • Condensed Matter Physics

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