Dipole controlled metal gate with hybrid low resistivity cladding for gate-last CMOS with low Vt

Christopher L. Hinkle; Rohit V. Galatage; Richard A. Chapman; Eric M. Vogel; Husam N. Alshareef; Clive M. Freeman; Erich Wimmer; Hiroaki Niimi; Andrei V. Li-Fatou; Judy B. Shaw; James J. Chambers

doi:10.1109/VLSIT.2010.5556220

Dipole controlled metal gate with hybrid low resistivity cladding for gate-last CMOS with low Vt

Christopher L. Hinkle, Rohit V. Galatage, Richard A. Chapman, Eric M. Vogel, Husam N. Alshareef, Clive M. Freeman, Erich Wimmer, Hiroaki Niimi, Andrei V. Li-Fatou, Judy B. Shaw, James J. Chambers

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

16 Scopus citations

Abstract

In this contribution, NMOS and PMOS band edge effective work function (EWF) and correspondingly low Vt are demonstrated using standard fab materials and processes in a gate-last scheme. For NMOS, the use of an Al cladding layer results in Vt = 0.08 V consistent with NMOS EWF = 4.15 eV. Migration of the Al cladding into the TiN and a relatively low oxygen concentration near the TiN/HfO2 interface are responsible for the low EWF. For PMOS, employing a W cladding layer along with a post-TiN anneal in an oxidizing ambient results in elevated oxygen concentration near the TiN/HfO2 interface and Vt = -0.20 V consistent with a PMOS EWF = 5.05 eV. First-principles calculations indicate N atoms displaced from the TiN during the oxidizing anneal form dipoles at the TiN/HfO2 interface that play a critical role in determining the PMOS EWF. © 2010 IEEE.

Original language	English (US)
Title of host publication	2010 Symposium on VLSI Technology
Publisher	Institute of Electrical and Electronics Engineers (IEEE)
Pages	183-184
Number of pages	2
ISBN (Print)	9781424476374
DOIs	https://doi.org/10.1109/VLSIT.2010.5556220
State	Published - Jun 2010

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Hinkle, C. L., Galatage, R. V., Chapman, R. A., Vogel, E. M., Alshareef, H. N., Freeman, C. M., Wimmer, E., Niimi, H., Li-Fatou, A. V., Shaw, J. B., & Chambers, J. J. (2010). Dipole controlled metal gate with hybrid low resistivity cladding for gate-last CMOS with low Vt. In 2010 Symposium on VLSI Technology (pp. 183-184). Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/VLSIT.2010.5556220

@inproceedings{8cf9bf31e45e4128985155c723addcd7,

title = "Dipole controlled metal gate with hybrid low resistivity cladding for gate-last CMOS with low Vt",

abstract = "In this contribution, NMOS and PMOS band edge effective work function (EWF) and correspondingly low Vt are demonstrated using standard fab materials and processes in a gate-last scheme. For NMOS, the use of an Al cladding layer results in Vt = 0.08 V consistent with NMOS EWF = 4.15 eV. Migration of the Al cladding into the TiN and a relatively low oxygen concentration near the TiN/HfO2 interface are responsible for the low EWF. For PMOS, employing a W cladding layer along with a post-TiN anneal in an oxidizing ambient results in elevated oxygen concentration near the TiN/HfO2 interface and Vt = -0.20 V consistent with a PMOS EWF = 5.05 eV. First-principles calculations indicate N atoms displaced from the TiN during the oxidizing anneal form dipoles at the TiN/HfO2 interface that play a critical role in determining the PMOS EWF. {\textcopyright} 2010 IEEE.",

author = "Hinkle, {Christopher L.} and Galatage, {Rohit V.} and Chapman, {Richard A.} and Vogel, {Eric M.} and Alshareef, {Husam N.} and Freeman, {Clive M.} and Erich Wimmer and Hiroaki Niimi and Li-Fatou, {Andrei V.} and Shaw, {Judy B.} and Chambers, {James J.}",

note = "KAUST Repository Item: Exported on 2020-10-01",

year = "2010",

month = jun,

doi = "10.1109/VLSIT.2010.5556220",

language = "English (US)",

isbn = "9781424476374",

pages = "183--184",

booktitle = "2010 Symposium on VLSI Technology",

publisher = "Institute of Electrical and Electronics Engineers (IEEE)",

}

Hinkle, CL, Galatage, RV, Chapman, RA, Vogel, EM, Alshareef, HN, Freeman, CM, Wimmer, E, Niimi, H, Li-Fatou, AV, Shaw, JB & Chambers, JJ 2010, Dipole controlled metal gate with hybrid low resistivity cladding for gate-last CMOS with low Vt. in 2010 Symposium on VLSI Technology. Institute of Electrical and Electronics Engineers (IEEE), pp. 183-184. https://doi.org/10.1109/VLSIT.2010.5556220

Dipole controlled metal gate with hybrid low resistivity cladding for gate-last CMOS with low Vt. / Hinkle, Christopher L.; Galatage, Rohit V.; Chapman, Richard A. et al.
2010 Symposium on VLSI Technology. Institute of Electrical and Electronics Engineers (IEEE), 2010. p. 183-184.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Dipole controlled metal gate with hybrid low resistivity cladding for gate-last CMOS with low Vt

AU - Hinkle, Christopher L.

AU - Galatage, Rohit V.

AU - Chapman, Richard A.

AU - Vogel, Eric M.

AU - Alshareef, Husam N.

AU - Freeman, Clive M.

AU - Wimmer, Erich

AU - Niimi, Hiroaki

AU - Li-Fatou, Andrei V.

AU - Shaw, Judy B.

AU - Chambers, James J.

N1 - KAUST Repository Item: Exported on 2020-10-01

PY - 2010/6

Y1 - 2010/6

N2 - In this contribution, NMOS and PMOS band edge effective work function (EWF) and correspondingly low Vt are demonstrated using standard fab materials and processes in a gate-last scheme. For NMOS, the use of an Al cladding layer results in Vt = 0.08 V consistent with NMOS EWF = 4.15 eV. Migration of the Al cladding into the TiN and a relatively low oxygen concentration near the TiN/HfO2 interface are responsible for the low EWF. For PMOS, employing a W cladding layer along with a post-TiN anneal in an oxidizing ambient results in elevated oxygen concentration near the TiN/HfO2 interface and Vt = -0.20 V consistent with a PMOS EWF = 5.05 eV. First-principles calculations indicate N atoms displaced from the TiN during the oxidizing anneal form dipoles at the TiN/HfO2 interface that play a critical role in determining the PMOS EWF. © 2010 IEEE.

AB - In this contribution, NMOS and PMOS band edge effective work function (EWF) and correspondingly low Vt are demonstrated using standard fab materials and processes in a gate-last scheme. For NMOS, the use of an Al cladding layer results in Vt = 0.08 V consistent with NMOS EWF = 4.15 eV. Migration of the Al cladding into the TiN and a relatively low oxygen concentration near the TiN/HfO2 interface are responsible for the low EWF. For PMOS, employing a W cladding layer along with a post-TiN anneal in an oxidizing ambient results in elevated oxygen concentration near the TiN/HfO2 interface and Vt = -0.20 V consistent with a PMOS EWF = 5.05 eV. First-principles calculations indicate N atoms displaced from the TiN during the oxidizing anneal form dipoles at the TiN/HfO2 interface that play a critical role in determining the PMOS EWF. © 2010 IEEE.

UR - http://hdl.handle.net/10754/564284

UR - http://ieeexplore.ieee.org/document/5556220/

UR - http://www.scopus.com/inward/record.url?scp=77957862779&partnerID=8YFLogxK

U2 - 10.1109/VLSIT.2010.5556220

DO - 10.1109/VLSIT.2010.5556220

M3 - Conference contribution

SN - 9781424476374

SP - 183

EP - 184

BT - 2010 Symposium on VLSI Technology

PB - Institute of Electrical and Electronics Engineers (IEEE)

ER -

Dipole controlled metal gate with hybrid low resistivity cladding for gate-last CMOS with low Vt

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