Development of barrier slurry for improved electrical performance

L. S. Leong, Jason J. Keleher, B. F. Lin, X. B. Wang, P. P. Yap, Feng Zhao, M. S. Zhou, Albert Lau

Research output: Contribution to journalArticlepeer-review

2 Scopus citations


As device dimensions shrink to the sub-65 nm regime, a greater demand is placed upon the barrier polishing process. Therefore the ability to modulate the barrier chemical mechanical planarization performance window by process and formulation synergy can provide tunability at advanced technology nodes to meet stringent electrical, topography, and defect requirements. This study introduces one approach in achieving the synergy between barrier polishing slurry and the development of a robust process. The system investigated has demonstrated desirable Rs uniformity control and greater margin for polishing. Extensive Mx layer testing (more than 10 wafer lots) has consistently shown better within-wafer Rs (resistance) spread compared to process of record, with improvement above 30% for all layers. The slurry also shows a more gradual Rs fluctuation over a 20 s polish time range. A marathon run has also shown consistent polishing rate performance over the pad life with comparable defect density and characteristics.

Original languageEnglish (US)
Pages (from-to)H756-H761
Issue number9
StatePublished - 2009

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Renewable Energy, Sustainability and the Environment
  • Surfaces, Coatings and Films
  • Electrochemistry
  • Materials Chemistry


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