Design of CMOS-memristor Circuits for LSTM architecture

Kamilya Smagulova, Kazybek Adam, Olga Krestinskaya, Alex Pappachen James

Research output: Chapter in Book/Report/Conference proceedingConference contribution

15 Scopus citations


Long Short-Term memory (LSTM) architecture is a well-known approach for building recurrent neural networks (RNN) useful in sequential processing of data in application to natural language processing. The near-sensor hardware implementation of LSTM is challenged due to large parallelism and complexity. We propose a 0.18 μ m CMOS, GST memristor LSTM hardware architecture for near-sensor processing. The proposed system is validated in a forecasting problem based on Keras model.
Original languageEnglish (US)
Title of host publication2018 IEEE International Conference on Electron Devices and Solid State Circuits, EDSSC 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781538662342
StatePublished - Oct 9 2018
Externally publishedYes

Bibliographical note

Generated from Scopus record by KAUST IRTS on 2023-09-23


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