Design of a low power 10-b 8-ms/s asynchronous SAR adc with on-chip reference voltage generator

Khuram Shehzad, Deeksha Verma, Danial Khan, Qurat Ul Ain, Muhammad Basim, Sung Jin Kim, Younggun Pu, Keum Cheol Hwang, Youngoo Yang, Kang Yoon Lee

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13 Scopus citations


This paper presents an energy-efficient low power 10-b 8-MS/s asynchronous successive approximation register (SAR) analog-to-digital (ADC) converter. An inverted common-mode charge recovery technique is proposed to reduce the switching energy and to improve the linearity of the digital-to-analog converter (DAC). The proposed switching technique consumes only 149 CVREF 2 switching energy for the 10-bit case. A rail-to-rail dynamic latch comparator is implemented with adaptive power control for better power efficiency. Additionally, to optimize the power consumption and performance of the logic part, a modified asynchronous type SAR control logic with digitally controllable delay cells is adopted. An on-chip reference voltage generator is also designed with an ADC core for practical use. The structure is realized using 55-nm complementary metal–oxide–semiconductor (CMOS) process technology. The proposed architecture achieves an effective number of bits (ENOB) of 9.56 bits and a signal-to-noise and distortion ratio (SNDR) level of 59.3 dB with a sampling rate of 8 MS/s at measurement level. The whole architecture consumes only 572 µW power when a power supply of 1 V is applied.
Original languageEnglish (US)
JournalElectronics (Switzerland)
Issue number5
StatePublished - May 1 2020
Externally publishedYes

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Generated from Scopus record by KAUST IRTS on 2023-09-23


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