Design of a capacitor-less LDO with high PSRR for RF energy harvesting applications

Danial Khan; Hamed Abbasizadeh; Zaffar Hayat Nawaz Khan; Young Jun Park; Kang Yoon Lee

doi:10.1109/ISOCC.2017.8368852

Design of a capacitor-less LDO with high PSRR for RF energy harvesting applications

Danial Khan, Hamed Abbasizadeh, Zaffar Hayat Nawaz Khan, Young Jun Park, Kang Yoon Lee

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Scopus citations

Abstract

This paper presents a capacitor-less low-dropout (LDO) regulators with high power supply rejection ratio (PSRR) for powering RF energy harvesting applications. The band-gap reference (BGR) in the proposed LDO utilizes a current mode regulator to isolate the band-gap reference circuitry from supply variations and noise. The proposed LDO achieves a high post-layout simulated PSRR of -85.67dB at 1 kHz. The proposed LDO is implemented in a standard 180nm CMOS technology with the die size of 378μm × 390μm.

Original language	English (US)
Title of host publication	Proceedings - International SoC Design Conference 2017, ISOCC 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	202-203
Number of pages	2
ISBN (Print)	9781538622858
DOIs	https://doi.org/10.1109/ISOCC.2017.8368852
State	Published - May 29 2018
Externally published	Yes

Bibliographical note

Generated from Scopus record by KAUST IRTS on 2023-09-23

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10.1109/ISOCC.2017.8368852

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title = "Design of a capacitor-less LDO with high PSRR for RF energy harvesting applications",

abstract = "This paper presents a capacitor-less low-dropout (LDO) regulators with high power supply rejection ratio (PSRR) for powering RF energy harvesting applications. The band-gap reference (BGR) in the proposed LDO utilizes a current mode regulator to isolate the band-gap reference circuitry from supply variations and noise. The proposed LDO achieves a high post-layout simulated PSRR of -85.67dB at 1 kHz. The proposed LDO is implemented in a standard 180nm CMOS technology with the die size of 378μm × 390μm.",

author = "Danial Khan and Hamed Abbasizadeh and Khan, {Zaffar Hayat Nawaz} and Park, {Young Jun} and Lee, {Kang Yoon}",

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month = may,

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doi = "10.1109/ISOCC.2017.8368852",

language = "English (US)",

isbn = "9781538622858",

pages = "202--203",

booktitle = "Proceedings - International SoC Design Conference 2017, ISOCC 2017",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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}

Design of a capacitor-less LDO with high PSRR for RF energy harvesting applications. / Khan, Danial; Abbasizadeh, Hamed; Khan, Zaffar Hayat Nawaz et al.
Proceedings - International SoC Design Conference 2017, ISOCC 2017. Institute of Electrical and Electronics Engineers Inc., 2018. p. 202-203.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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T1 - Design of a capacitor-less LDO with high PSRR for RF energy harvesting applications

AU - Khan, Danial

AU - Abbasizadeh, Hamed

AU - Khan, Zaffar Hayat Nawaz

AU - Park, Young Jun

AU - Lee, Kang Yoon

N1 - Generated from Scopus record by KAUST IRTS on 2023-09-23

PY - 2018/5/29

Y1 - 2018/5/29

N2 - This paper presents a capacitor-less low-dropout (LDO) regulators with high power supply rejection ratio (PSRR) for powering RF energy harvesting applications. The band-gap reference (BGR) in the proposed LDO utilizes a current mode regulator to isolate the band-gap reference circuitry from supply variations and noise. The proposed LDO achieves a high post-layout simulated PSRR of -85.67dB at 1 kHz. The proposed LDO is implemented in a standard 180nm CMOS technology with the die size of 378μm × 390μm.

AB - This paper presents a capacitor-less low-dropout (LDO) regulators with high power supply rejection ratio (PSRR) for powering RF energy harvesting applications. The band-gap reference (BGR) in the proposed LDO utilizes a current mode regulator to isolate the band-gap reference circuitry from supply variations and noise. The proposed LDO achieves a high post-layout simulated PSRR of -85.67dB at 1 kHz. The proposed LDO is implemented in a standard 180nm CMOS technology with the die size of 378μm × 390μm.

UR - https://ieeexplore.ieee.org/document/8368852/

UR - http://www.scopus.com/inward/record.url?scp=85048874718&partnerID=8YFLogxK

U2 - 10.1109/ISOCC.2017.8368852

DO - 10.1109/ISOCC.2017.8368852

M3 - Conference contribution

SN - 9781538622858

SP - 202

EP - 203

BT - Proceedings - International SoC Design Conference 2017, ISOCC 2017

PB - Institute of Electrical and Electronics Engineers Inc.

ER -

Design of a capacitor-less LDO with high PSRR for RF energy harvesting applications

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