In the past two decades, wavelet method has emerged as a powerful signal and data analysis tool for scientist and engineers. It is often part of a low-power system for real time application and needs efficient hardware implementation. In this paper, we have designed and VLSI (Very Large-Scale In-tegration) implemented a lossless 5/3 Discrete Wavelet Transform (DWT) using the Canonical Signed Digit (CSD) based Distributed Arithmetic (DA) architecture. The combination of CSD and DA exploits prior knowledge of the filter co-efficients and uses the least number of adders and shift registers, to achieve hardware-efficient implementation. The filter-based implementation exploits data path diagram of CSD represented coefficients and selectively finds sum of products to give minimum realization. The proposed CSD based DA architecture is modeled using HDL (Hardware Description Language) and implemented on Altera DE-1 Cyclon-II FPGA (Field Programmable Gate Array). A comparison with filter-based architecture of 5/3 DWT reveals a saving up to 50% in hardware. The designed solution is hardware efficient and uses only 7 adders to provide low-power architecture for high-speed real-time applications.
|Title of host publication
|Proceedings of 2019 16th International Bhurban Conference on Applied Sciences and Technology, IBCAST 2019
|Institute of Electrical and Electronics Engineers Inc.
|Number of pages
|Published - Mar 13 2019