Design and Implementation of a Sort-Free K-Best Sphere Decoder

Sudip Mondal, Ahmed M. Eltawil, Chung-An Shen, Khaled N. Salama

Research output: Contribution to journalArticlepeer-review

63 Scopus citations


This paper describes the design and VLSI architecture for a 4x4 breadth first K-Best MIMO decoder using a 64 QAM scheme. A novel sort free approach to path extension, as well as quantized metrics result in a high throughput VLSI architecture with lower power and area consumption compared to state of the art published systems. Functionality is confirmed via an FPGA implementation on a Xilinx Virtex II Pro FPGA. Comparison of simulation and measurements are given and FPGA utilization figures are provided. Finally, VLSI architectural tradeoffs are explored for a synthesized ASIC implementation in a 65nm CMOS technology.
Original languageEnglish (US)
Pages (from-to)1497-1501
Number of pages5
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number10
StatePublished - Nov 13 2009

Bibliographical note

KAUST Repository Item: Exported on 2020-10-01


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