TY - JOUR
T1 - Design and implementation of a baseband WCDMA dual-antenna mobile terminal
AU - Frigon, Jean François
AU - Eltawil, Ahmed M.
AU - Grayver, Eugene
AU - Tarighat, Alireza
AU - Zou, Hanli
N1 - Generated from Scopus record by KAUST IRTS on 2019-11-20
PY - 2007/3/1
Y1 - 2007/3/1
N2 - The design and implementation of a baseband wide-band code-division multiple access (WCDMA) dual-antenna mobile terminal system-on-a-chip (SoC) is presented in this paper. Spatial diversity processing mitigates wireless channel impairments and is a key enabling technology for WCDMA to support high quality of service at high data rates and capacity. The SoC integrates the baseband transceiver, coding and decoding functions, microcontrollers to implement the radio access protocols, and external interfaces to communicate with the application layer. The receiver design, which takes advantage of diversity benefits in several blocks, is described in detail. The SoC was fabricated in a 0.18-μm 1.8-V CMOS technology and requires a total area of 72 mm2 consuming 532 mW at the maximum data rates. The application-specific integrated circuit was used in lab testing where a gain of up to 9 dB was observed for the dual-antenna receiver, which demonstrates the tremendous improvement provided by spatial diversity. The results presented in this paper provide a base architecture and a performance benchmark for commercial implementations of WCDMA mobile terminals. © 2007 IEEE.
AB - The design and implementation of a baseband wide-band code-division multiple access (WCDMA) dual-antenna mobile terminal system-on-a-chip (SoC) is presented in this paper. Spatial diversity processing mitigates wireless channel impairments and is a key enabling technology for WCDMA to support high quality of service at high data rates and capacity. The SoC integrates the baseband transceiver, coding and decoding functions, microcontrollers to implement the radio access protocols, and external interfaces to communicate with the application layer. The receiver design, which takes advantage of diversity benefits in several blocks, is described in detail. The SoC was fabricated in a 0.18-μm 1.8-V CMOS technology and requires a total area of 72 mm2 consuming 532 mW at the maximum data rates. The application-specific integrated circuit was used in lab testing where a gain of up to 9 dB was observed for the dual-antenna receiver, which demonstrates the tremendous improvement provided by spatial diversity. The results presented in this paper provide a base architecture and a performance benchmark for commercial implementations of WCDMA mobile terminals. © 2007 IEEE.
UR - http://ieeexplore.ieee.org/document/4126792/
UR - http://www.scopus.com/inward/record.url?scp=34047181031&partnerID=8YFLogxK
U2 - 10.1109/TCSI.2006.887620
DO - 10.1109/TCSI.2006.887620
M3 - Article
SN - 1057-7122
VL - 54
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 3
ER -