In this work, a novel design strategy and experimental results of a micro-electro-mechanical system (MEMS) resonator-based 7:3 compressor, the core building block of digital multipliers, are presented. The compressor consists of three identical clamped-clamped beam resonators and an auxiliary complementary-metal-oxide-semi-conductor (CMOS) summing amplifier. The compressor is designed such that the seven input bits tune the resonance frequencies of the resonators using the electrostatic softening effect. Each resonator is driven by four different frequencies to generate one of the output bits. Experimental results are obtained to verify the compressor operation. The overall design complexity and interconnect overhead of the proposed compressor, even considering the amplifier, is significantly reduced compared to the CMOS-only compressors which require more than 100 transistors on average. The energy consumption of the resonators used in the design is around 59.01 pJ/Op with a sampling rate of 80 S/s. We show that by scaling and optimizing the device dimension, lower energy, and kS/s sampling rate are attainable.