This work presents measured results from test chips containing circuits implemented with micro-electro-mechanical (MEM) relays. The relay circuits designed on these test chips illustrate a range of important functions necessary for the implementation of integrated VLSI systems and lend insight into circuit design techniques optimized for the physical properties of these devices. To explore these techniques a hybrid electro-mechanical model of the relays' electrical and mechanical characteristics has been developed, correlated to measurements, and then also applied to predict MEM relay performance if the technology were scaled to a 90 nm technology node. A theoretical, scaled, 32-bit MEM relay-based adder, with a single-bit functionality demonstrated by the measured circuits, is found to offer a factor of ten energy efficiency gain over an optimized CMOS adder for sub-20 MOPS throughputs at a moderate increase in area.
Bibliographical noteFunding Information:
Manuscript received April 20, 2010; revised July 05, 2010; accepted July 16, 2010. Date of publication November 01, 2010; date of current version December 27, 2010. This paper was approved by Guest Editor Alison Burdett. This work was supported in part by the DARPA NEMS program, the C2S2 and MSD FCRP centers, MIT CICS, UCLA ICSL, BWRC, and NSF Infrastructure Grant No. 040327.
- MEM relays
- digital circuits
- microelectromechanical devices
- minimum energy point
- very-large-scale integration
ASJC Scopus subject areas
- Electrical and Electronic Engineering