Crystalline Complex Oxide Membrane: Sub-1 nm CET Dielectrics for 2D Transistors

Jing-Kai Huang; Yi Wan; Junjie Shi; Ji Zhang; Zeheng Wang; Zi-Liang Yang; Bo-Chao Huang; Ya-Ping Chiu; Wenxuan Wang; Ni Yang; Yang Liu; Chun-Ho Lin; Xinwei Guan; Long Hu; Jack Yang; Danyang Wang; Vincent Tung; Kourosh Kalantar-Zadeh; Tom Wu; Xiaotao Zu; Liang Qiao; Sean Li; Lain-Jong Li

doi:10.1109/iedm45625.2022.10019466

Crystalline Complex Oxide Membrane: Sub-1 nm CET Dielectrics for 2D Transistors

Jing-Kai Huang, Yi Wan, Junjie Shi, Ji Zhang, Zeheng Wang, Zi-Liang Yang, Bo-Chao Huang, Ya-Ping Chiu, Wenxuan Wang, Ni Yang, Yang Liu, Chun-Ho Lin, Xinwei Guan, Long Hu, Jack Yang, Danyang Wang, Vincent Tung, Kourosh Kalantar-Zadeh, Tom Wu, Xiaotao ZuLiang Qiao, Sean Li, Lain-Jong Li

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Scopus citations

Abstract

Atomically thin 2D semiconductors have been regarded as promising candidates for the channels in ultra-scaled transistors. Although high-performance 2D field-effect transistors (FETs) have been demonstrated, the integration with conventional high-κ gate insulators is yet to be improved for energy-efficient devices. Here, 2D FETs with sub-1 nm capacitance equivalent thickness (CET) are demonstrated through the integration of transferrable single-crystal SrTiO 3 thin dielectrics with a monolayer CVD MoS 2 , where the optimized SrTiO 3 gate stack exhibits a gate leakage far below the low-standby-power limit (1.5×10 -2 A/cm 2 ). The short-channel devices manifest good reliability and competitive performance characteristics, including the steep subthreshold swing (SS) down to ~75 mV dec -1 and a large ON/OFF current ratio of 10 6 .

Original language	English (US)
Title of host publication	2022 International Electron Devices Meeting (IEDM)
Publisher	IEEE
DOIs	https://doi.org/10.1109/iedm45625.2022.10019466
State	Published - Jan 23 2023

Bibliographical note

KAUST Repository Item: Exported on 2023-01-31
Acknowledgements: The authors acknowledge the support from UNSW Sydney, The University of Hong Kong, and National Taiwan University.

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10.1109/iedm45625.2022.10019466

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Huang, J.-K., Wan, Y., Shi, J., Zhang, J., Wang, Z., Yang, Z.-L., Huang, B.-C., Chiu, Y.-P., Wang, W., Yang, N., Liu, Y., Lin, C.-H., Guan, X., Hu, L., Yang, J., Wang, D., Tung, V., Kalantar-Zadeh, K., Wu, T., ... Li, L.-J. (2023). Crystalline Complex Oxide Membrane: Sub-1 nm CET Dielectrics for 2D Transistors. In 2022 International Electron Devices Meeting (IEDM) IEEE. https://doi.org/10.1109/iedm45625.2022.10019466

@inproceedings{da4286e10fc34a618372db4c27d41abf,

title = "Crystalline Complex Oxide Membrane: Sub-1 nm CET Dielectrics for 2D Transistors",

abstract = "Atomically thin 2D semiconductors have been regarded as promising candidates for the channels in ultra-scaled transistors. Although high-performance 2D field-effect transistors (FETs) have been demonstrated, the integration with conventional high-κ gate insulators is yet to be improved for energy-efficient devices. Here, 2D FETs with sub-1 nm capacitance equivalent thickness (CET) are demonstrated through the integration of transferrable single-crystal SrTiO 3 thin dielectrics with a monolayer CVD MoS 2 , where the optimized SrTiO 3 gate stack exhibits a gate leakage far below the low-standby-power limit (1.5×10 -2 A/cm 2 ). The short-channel devices manifest good reliability and competitive performance characteristics, including the steep subthreshold swing (SS) down to ~75 mV dec -1 and a large ON/OFF current ratio of 10 6 .",

author = "Jing-Kai Huang and Yi Wan and Junjie Shi and Ji Zhang and Zeheng Wang and Zi-Liang Yang and Bo-Chao Huang and Ya-Ping Chiu and Wenxuan Wang and Ni Yang and Yang Liu and Chun-Ho Lin and Xinwei Guan and Long Hu and Jack Yang and Danyang Wang and Vincent Tung and Kourosh Kalantar-Zadeh and Tom Wu and Xiaotao Zu and Liang Qiao and Sean Li and Lain-Jong Li",

note = "KAUST Repository Item: Exported on 2023-01-31 Acknowledgements: The authors acknowledge the support from UNSW Sydney, The University of Hong Kong, and National Taiwan University.",

year = "2023",

month = jan,

day = "23",

doi = "10.1109/iedm45625.2022.10019466",

language = "English (US)",

booktitle = "2022 International Electron Devices Meeting (IEDM)",

publisher = "IEEE",

}

Huang, J-K, Wan, Y, Shi, J, Zhang, J, Wang, Z, Yang, Z-L, Huang, B-C, Chiu, Y-P, Wang, W, Yang, N, Liu, Y, Lin, C-H, Guan, X, Hu, L, Yang, J, Wang, D, Tung, V, Kalantar-Zadeh, K, Wu, T, Zu, X, Qiao, L, Li, S & Li, L-J 2023, Crystalline Complex Oxide Membrane: Sub-1 nm CET Dielectrics for 2D Transistors. in 2022 International Electron Devices Meeting (IEDM). IEEE. https://doi.org/10.1109/iedm45625.2022.10019466

TY - GEN

T1 - Crystalline Complex Oxide Membrane: Sub-1 nm CET Dielectrics for 2D Transistors

AU - Huang, Jing-Kai

AU - Wan, Yi

AU - Shi, Junjie

AU - Zhang, Ji

AU - Wang, Zeheng

AU - Yang, Zi-Liang

AU - Huang, Bo-Chao

AU - Chiu, Ya-Ping

AU - Wang, Wenxuan

AU - Yang, Ni

AU - Liu, Yang

AU - Lin, Chun-Ho

AU - Guan, Xinwei

AU - Hu, Long

AU - Yang, Jack

AU - Wang, Danyang

AU - Tung, Vincent

AU - Kalantar-Zadeh, Kourosh

AU - Wu, Tom

AU - Zu, Xiaotao

AU - Qiao, Liang

AU - Li, Sean

AU - Li, Lain-Jong

N1 - KAUST Repository Item: Exported on 2023-01-31 Acknowledgements: The authors acknowledge the support from UNSW Sydney, The University of Hong Kong, and National Taiwan University.

PY - 2023/1/23

Y1 - 2023/1/23

N2 - Atomically thin 2D semiconductors have been regarded as promising candidates for the channels in ultra-scaled transistors. Although high-performance 2D field-effect transistors (FETs) have been demonstrated, the integration with conventional high-κ gate insulators is yet to be improved for energy-efficient devices. Here, 2D FETs with sub-1 nm capacitance equivalent thickness (CET) are demonstrated through the integration of transferrable single-crystal SrTiO 3 thin dielectrics with a monolayer CVD MoS 2 , where the optimized SrTiO 3 gate stack exhibits a gate leakage far below the low-standby-power limit (1.5×10 -2 A/cm 2 ). The short-channel devices manifest good reliability and competitive performance characteristics, including the steep subthreshold swing (SS) down to ~75 mV dec -1 and a large ON/OFF current ratio of 10 6 .

AB - Atomically thin 2D semiconductors have been regarded as promising candidates for the channels in ultra-scaled transistors. Although high-performance 2D field-effect transistors (FETs) have been demonstrated, the integration with conventional high-κ gate insulators is yet to be improved for energy-efficient devices. Here, 2D FETs with sub-1 nm capacitance equivalent thickness (CET) are demonstrated through the integration of transferrable single-crystal SrTiO 3 thin dielectrics with a monolayer CVD MoS 2 , where the optimized SrTiO 3 gate stack exhibits a gate leakage far below the low-standby-power limit (1.5×10 -2 A/cm 2 ). The short-channel devices manifest good reliability and competitive performance characteristics, including the steep subthreshold swing (SS) down to ~75 mV dec -1 and a large ON/OFF current ratio of 10 6 .

UR - http://hdl.handle.net/10754/687390

UR - https://ieeexplore.ieee.org/document/10019466/

U2 - 10.1109/iedm45625.2022.10019466

DO - 10.1109/iedm45625.2022.10019466

M3 - Conference contribution

BT - 2022 International Electron Devices Meeting (IEDM)

PB - IEEE

ER -

Crystalline Complex Oxide Membrane: Sub-1 nm CET Dielectrics for 2D Transistors

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