Crystalline Complex Oxide Membrane: Sub-1 nm CET Dielectrics for 2D Transistors

Jing-Kai Huang, Yi Wan, Junjie Shi, Ji Zhang, Zeheng Wang, Zi-Liang Yang, Bo-Chao Huang, Ya-Ping Chiu, Wenxuan Wang, Ni Yang, Yang Liu, Chun-Ho Lin, Xinwei Guan, Long Hu, Jack Yang, Danyang Wang, Vincent Tung, Kourosh Kalantar-Zadeh, Tom Wu, Xiaotao ZuLiang Qiao, Sean Li, Lain-Jong Li

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations


Atomically thin 2D semiconductors have been regarded as promising candidates for the channels in ultra-scaled transistors. Although high-performance 2D field-effect transistors (FETs) have been demonstrated, the integration with conventional high-κ gate insulators is yet to be improved for energy-efficient devices. Here, 2D FETs with sub-1 nm capacitance equivalent thickness (CET) are demonstrated through the integration of transferrable single-crystal SrTiO 3 thin dielectrics with a monolayer CVD MoS 2 , where the optimized SrTiO 3 gate stack exhibits a gate leakage far below the low-standby-power limit (1.5×10 -2 A/cm 2 ). The short-channel devices manifest good reliability and competitive performance characteristics, including the steep subthreshold swing (SS) down to ~75 mV dec -1 and a large ON/OFF current ratio of 10 6 .
Original languageEnglish (US)
Title of host publication2022 International Electron Devices Meeting (IEDM)
StatePublished - Jan 23 2023

Bibliographical note

KAUST Repository Item: Exported on 2023-01-31
Acknowledgements: The authors acknowledge the support from UNSW Sydney, The University of Hong Kong, and National Taiwan University.


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