In this paper, we investigate the crosstalk-induced delay, noise, and chemical mechanical polishing (CMP)-induced thickness-variation implications of dummy fill generated using rule-based wire track fill techniques and CMP-aware model-based methods for designs implemented in 65 nm process technology. The results indicate that fill generated using rule-based and CMP-aware model-based methods can have a significant impact on parasitic capacitance, interconnect planarization, and individual path delay variation. Crosstalk-induced delay and noise are significantly reduced in the grounded-fill cases, and designs with floating fill also experience a reduction in average crosstalk-induced delay and noise, which is in contrast to the predictions of previous studies on small-scale interconnect structures. When crosstalk effects are included in the analysis, the observed delay behavior is significantly different from the delay modeled without considering crosstalk effects. Consequently, crosstalk-induced delay and noise must be simultaneously considered in addition to parasitic capacitance and interconnect planarization when developing future fill generation methods. © 2009 IEEE.
|Original language||English (US)|
|Number of pages||14|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|State||Published - Mar 1 2010|
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering