Cross layer error exploitation for aggressive voltage scaling

Amin Khajeh Djahromi, Ahmed M. Eltawil, Fadi J. Kurdahi, Rouwaida Kanj

Research output: Chapter in Book/Report/Conference proceedingConference contribution

36 Scopus citations


This paper shows that by co-designing circuits and systems, considerable power savings are possible if the inherent data redundancy of candidate systems such as wireless is used to compensate for hardware failures. A comprehensive study of 6T SRAM failure modes is presented. The generated statistics are used to quantify a power savings of up to 17.5% for a case study of a 32 nm CMOS 3GPP WCDMA modem. © 2007 IEEE.
Original languageEnglish (US)
Title of host publicationProceedings - Eighth International Symposium on Quality Electronic Design, ISQED 2007
StatePublished - Aug 28 2007
Externally publishedYes

Bibliographical note

Generated from Scopus record by KAUST IRTS on 2019-11-20


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