Contact Engineering for High-Performance N-Type 2D Semiconductor Transistors

Y. Lin; P. C. Shen; C. Su; A. S. Chou; T. Wu; C. C. Cheng; J. H. Park; M. H. Chiu; A. Y. Lu; H. L. Tang; M. M. Tavakoli; G. Pitner; X. Ji; C. McGahan; X. Wang; Z. Cai; N. Mao; J. Wang; Y. Wang; W. Tisdale; X. Ling; K. E. Aidala; Vincent Tung; J. Li; A. Zettl; C. I. Wu; Jing Guo; H. Wang; J. Bokor; T. Palacios; L. J. Li; J. Kong

doi:10.1109/IEDM19574.2021.9720668

Contact Engineering for High-Performance N-Type 2D Semiconductor Transistors

Y. Lin, P. C. Shen, C. Su, A. S. Chou, T. Wu, C. C. Cheng, J. H. Park, M. H. Chiu, A. Y. Lu, H. L. Tang, M. M. Tavakoli, G. Pitner, X. Ji, C. McGahan, X. Wang, Z. Cai, N. Mao, J. Wang, Y. Wang, W. TisdaleX. Ling, K. E. Aidala, Vincent Tung, J. Li, A. Zettl, C. I. Wu, Jing Guo, H. Wang, J. Bokor, T. Palacios, L. J. Li, J. Kong

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Scopus citations

Abstract

Two-dimensional (2D) semiconductors are expected to have exceptional properties for ultimately scaled transistors, but forming ohmic contact to them has been challenging, which tremendously limit the transistor performance. In this paper, we review the recent research progress on the elimination of different gap-state pinning effects, including defect-induced gap states (DIGS) and metal-induced gap states (MIGS). Specifically, an oxygen passivation method and a semimetallic contact technology were developed to reduce the DIGS and MIGS, respectively. Based on these approaches, much improved contact resistance and on-state current were observed. Key device metrics were extracted on these high-performance transistors, which reveals future directions for further improving the device performance.

Original language	English (US)
Title of host publication	2021 IEEE International Electron Devices Meeting (IEDM)
Publisher	IEEE
Pages	37.2.1-37.2.4
ISBN (Print)	9781665425728
DOIs	https://doi.org/10.1109/IEDM19574.2021.9720668
State	Published - Dec 11 2021

Bibliographical note

KAUST Repository Item: Exported on 2022-12-12
Acknowledgements: This work is supported by NSF E3S Center 0939514, ARO MIT-ISN W911NF-18-2-0048, ONR MURI N00014-16-1-2921, NSF DMR-1839098, ARO W911NF-18-1-0431, DOE DE-AC02-05-CH11231, DOE DE-SC0020042, MOST 109-2622-8-002-003, TSMC JDP, NSF-DMR 1708970, SRC S4994.

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10.1109/IEDM19574.2021.9720668

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Lin, Y., Shen, P. C., Su, C., Chou, A. S., Wu, T., Cheng, C. C., Park, J. H., Chiu, M. H., Lu, A. Y., Tang, H. L., Tavakoli, M. M., Pitner, G., Ji, X., McGahan, C., Wang, X., Cai, Z., Mao, N., Wang, J., Wang, Y., ... Kong, J. (2021). Contact Engineering for High-Performance N-Type 2D Semiconductor Transistors. In 2021 IEEE International Electron Devices Meeting (IEDM) (pp. 37.2.1-37.2.4). IEEE. https://doi.org/10.1109/IEDM19574.2021.9720668

@inproceedings{a995eac7a45144fb8ecbdf02c056b54e,

title = "Contact Engineering for High-Performance N-Type 2D Semiconductor Transistors",

abstract = "Two-dimensional (2D) semiconductors are expected to have exceptional properties for ultimately scaled transistors, but forming ohmic contact to them has been challenging, which tremendously limit the transistor performance. In this paper, we review the recent research progress on the elimination of different gap-state pinning effects, including defect-induced gap states (DIGS) and metal-induced gap states (MIGS). Specifically, an oxygen passivation method and a semimetallic contact technology were developed to reduce the DIGS and MIGS, respectively. Based on these approaches, much improved contact resistance and on-state current were observed. Key device metrics were extracted on these high-performance transistors, which reveals future directions for further improving the device performance.",

author = "Y. Lin and Shen, {P. C.} and C. Su and Chou, {A. S.} and T. Wu and Cheng, {C. C.} and Park, {J. H.} and Chiu, {M. H.} and Lu, {A. Y.} and Tang, {H. L.} and Tavakoli, {M. M.} and G. Pitner and X. Ji and C. McGahan and X. Wang and Z. Cai and N. Mao and J. Wang and Y. Wang and W. Tisdale and X. Ling and Aidala, {K. E.} and Vincent Tung and J. Li and A. Zettl and Wu, {C. I.} and Jing Guo and H. Wang and J. Bokor and T. Palacios and Li, {L. J.} and J. Kong",

note = "KAUST Repository Item: Exported on 2022-12-12 Acknowledgements: This work is supported by NSF E3S Center 0939514, ARO MIT-ISN W911NF-18-2-0048, ONR MURI N00014-16-1-2921, NSF DMR-1839098, ARO W911NF-18-1-0431, DOE DE-AC02-05-CH11231, DOE DE-SC0020042, MOST 109-2622-8-002-003, TSMC JDP, NSF-DMR 1708970, SRC S4994.",

year = "2021",

month = dec,

day = "11",

doi = "10.1109/IEDM19574.2021.9720668",

language = "English (US)",

isbn = "9781665425728",

pages = "37.2.1--37.2.4",

booktitle = "2021 IEEE International Electron Devices Meeting (IEDM)",

publisher = "IEEE",

}

Lin, Y, Shen, PC, Su, C, Chou, AS, Wu, T, Cheng, CC, Park, JH, Chiu, MH, Lu, AY, Tang, HL, Tavakoli, MM, Pitner, G, Ji, X, McGahan, C, Wang, X, Cai, Z, Mao, N, Wang, J, Wang, Y, Tisdale, W, Ling, X, Aidala, KE, Tung, V, Li, J, Zettl, A, Wu, CI, Guo, J, Wang, H, Bokor, J, Palacios, T, Li, LJ & Kong, J 2021, Contact Engineering for High-Performance N-Type 2D Semiconductor Transistors. in 2021 IEEE International Electron Devices Meeting (IEDM). IEEE, pp. 37.2.1-37.2.4. https://doi.org/10.1109/IEDM19574.2021.9720668

TY - GEN

T1 - Contact Engineering for High-Performance N-Type 2D Semiconductor Transistors

AU - Lin, Y.

AU - Shen, P. C.

AU - Su, C.

AU - Chou, A. S.

AU - Wu, T.

AU - Cheng, C. C.

AU - Park, J. H.

AU - Chiu, M. H.

AU - Lu, A. Y.

AU - Tang, H. L.

AU - Tavakoli, M. M.

AU - Pitner, G.

AU - Ji, X.

AU - McGahan, C.

AU - Wang, X.

AU - Cai, Z.

AU - Mao, N.

AU - Wang, J.

AU - Wang, Y.

AU - Tisdale, W.

AU - Ling, X.

AU - Aidala, K. E.

AU - Tung, Vincent

AU - Li, J.

AU - Zettl, A.

AU - Wu, C. I.

AU - Guo, Jing

AU - Wang, H.

AU - Bokor, J.

AU - Palacios, T.

AU - Li, L. J.

AU - Kong, J.

N1 - KAUST Repository Item: Exported on 2022-12-12 Acknowledgements: This work is supported by NSF E3S Center 0939514, ARO MIT-ISN W911NF-18-2-0048, ONR MURI N00014-16-1-2921, NSF DMR-1839098, ARO W911NF-18-1-0431, DOE DE-AC02-05-CH11231, DOE DE-SC0020042, MOST 109-2622-8-002-003, TSMC JDP, NSF-DMR 1708970, SRC S4994.

PY - 2021/12/11

Y1 - 2021/12/11

N2 - Two-dimensional (2D) semiconductors are expected to have exceptional properties for ultimately scaled transistors, but forming ohmic contact to them has been challenging, which tremendously limit the transistor performance. In this paper, we review the recent research progress on the elimination of different gap-state pinning effects, including defect-induced gap states (DIGS) and metal-induced gap states (MIGS). Specifically, an oxygen passivation method and a semimetallic contact technology were developed to reduce the DIGS and MIGS, respectively. Based on these approaches, much improved contact resistance and on-state current were observed. Key device metrics were extracted on these high-performance transistors, which reveals future directions for further improving the device performance.

AB - Two-dimensional (2D) semiconductors are expected to have exceptional properties for ultimately scaled transistors, but forming ohmic contact to them has been challenging, which tremendously limit the transistor performance. In this paper, we review the recent research progress on the elimination of different gap-state pinning effects, including defect-induced gap states (DIGS) and metal-induced gap states (MIGS). Specifically, an oxygen passivation method and a semimetallic contact technology were developed to reduce the DIGS and MIGS, respectively. Based on these approaches, much improved contact resistance and on-state current were observed. Key device metrics were extracted on these high-performance transistors, which reveals future directions for further improving the device performance.

UR - http://hdl.handle.net/10754/676098

UR - https://ieeexplore.ieee.org/document/9720668/

UR - http://www.scopus.com/inward/record.url?scp=85126947629&partnerID=8YFLogxK

U2 - 10.1109/IEDM19574.2021.9720668

DO - 10.1109/IEDM19574.2021.9720668

M3 - Conference contribution

SN - 9781665425728

SP - 37.2.1-37.2.4

BT - 2021 IEEE International Electron Devices Meeting (IEDM)

PB - IEEE

ER -

Contact Engineering for High-Performance N-Type 2D Semiconductor Transistors

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