Abstract
Leakage current is one of the main challenges facing high-density MOS-gated memristor arrays. In this study, we show that leakage current ruins the memory readout process for high-density arrays, and analyze the tradeoff between the array density and its power consumption. We propose a novel readout technique and its underlying circuitry, which is able to compensate for the transistor leakage-current effect in the high-density gated memristor array.
Original language | English (US) |
---|---|
Pages (from-to) | 3-6 |
Number of pages | 4 |
Journal | IEEE Transactions on Nanotechnology |
Volume | 14 |
Issue number | 1 |
DOIs | |
State | Published - Jan 2015 |
Bibliographical note
KAUST Repository Item: Exported on 2020-10-01ASJC Scopus subject areas
- Computer Science Applications
- Electrical and Electronic Engineering