Comparative Analysis of Vertically Stacked Nanosheet FET based SONOS Memory

Md Hasan Raza Ansari; Nazek El-Atab

doi:10.1109/SNW56633.2022.9889062

Comparative Analysis of Vertically Stacked Nanosheet FET based SONOS Memory

Md Hasan Raza Ansari, Nazek El-Atab^*

^*Corresponding author for this work

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This work presents vertically stacked Nanosheet Field-Effect Transistors based SONOS memory cell and highlights the effect of vertically stacking sheets on the memory performance. Thanks to the gate all around structure, the Program and Erase operations are performed via F-N tunneling using faster (10 μs) and lower voltages (9 V and -8 V, respectively) due to the higher electric field across the tunneling oxide (Eox) compared to planar devices. Moreover, the results show that increasing the number of stacked nanosheets boosts the drain current but with a negligible effect on the memory window due to the same Eox.

Original language	English (US)
Title of host publication	2022 IEEE Silicon Nanoelectronics Workshop, SNW 2022
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781665459792
DOIs	https://doi.org/10.1109/SNW56633.2022.9889062
State	Published - 2022
Event	2022 IEEE Silicon Nanoelectronics Workshop, SNW 2022 - Honolulu, United States Duration: Jun 11 2022 → Jun 12 2022

Publication series

Name	2022 IEEE Silicon Nanoelectronics Workshop, SNW 2022

Conference

Conference	2022 IEEE Silicon Nanoelectronics Workshop, SNW 2022
Country/Territory	United States
City	Honolulu
Period	06/11/22 → 06/12/22

Bibliographical note

Publisher Copyright:
© 2022 IEEE.

ASJC Scopus subject areas

Hardware and Architecture
Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality
Electronic, Optical and Magnetic Materials

Access to Document

10.1109/SNW56633.2022.9889062

Cite this

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title = "Comparative Analysis of Vertically Stacked Nanosheet FET based SONOS Memory",

abstract = "This work presents vertically stacked Nanosheet Field-Effect Transistors based SONOS memory cell and highlights the effect of vertically stacking sheets on the memory performance. Thanks to the gate all around structure, the Program and Erase operations are performed via F-N tunneling using faster (10 μs) and lower voltages (9 V and -8 V, respectively) due to the higher electric field across the tunneling oxide (Eox) compared to planar devices. Moreover, the results show that increasing the number of stacked nanosheets boosts the drain current but with a negligible effect on the memory window due to the same Eox.",

author = "Ansari, {Md Hasan Raza} and Nazek El-Atab",

note = "Publisher Copyright: {\textcopyright} 2022 IEEE.; 2022 IEEE Silicon Nanoelectronics Workshop, SNW 2022 ; Conference date: 11-06-2022 Through 12-06-2022",

year = "2022",

doi = "10.1109/SNW56633.2022.9889062",

language = "English (US)",

series = "2022 IEEE Silicon Nanoelectronics Workshop, SNW 2022",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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}

Ansari, MHR & El-Atab, N 2022, Comparative Analysis of Vertically Stacked Nanosheet FET based SONOS Memory. in 2022 IEEE Silicon Nanoelectronics Workshop, SNW 2022. 2022 IEEE Silicon Nanoelectronics Workshop, SNW 2022, Institute of Electrical and Electronics Engineers Inc., 2022 IEEE Silicon Nanoelectronics Workshop, SNW 2022, Honolulu, United States, 06/11/22. https://doi.org/10.1109/SNW56633.2022.9889062

Comparative Analysis of Vertically Stacked Nanosheet FET based SONOS Memory. / Ansari, Md Hasan Raza ; El-Atab, Nazek.
2022 IEEE Silicon Nanoelectronics Workshop, SNW 2022. Institute of Electrical and Electronics Engineers Inc., 2022. (2022 IEEE Silicon Nanoelectronics Workshop, SNW 2022).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Ansari, Md Hasan Raza

AU - El-Atab, Nazek

PY - 2022

Y1 - 2022

N2 - This work presents vertically stacked Nanosheet Field-Effect Transistors based SONOS memory cell and highlights the effect of vertically stacking sheets on the memory performance. Thanks to the gate all around structure, the Program and Erase operations are performed via F-N tunneling using faster (10 μs) and lower voltages (9 V and -8 V, respectively) due to the higher electric field across the tunneling oxide (Eox) compared to planar devices. Moreover, the results show that increasing the number of stacked nanosheets boosts the drain current but with a negligible effect on the memory window due to the same Eox.

AB - This work presents vertically stacked Nanosheet Field-Effect Transistors based SONOS memory cell and highlights the effect of vertically stacking sheets on the memory performance. Thanks to the gate all around structure, the Program and Erase operations are performed via F-N tunneling using faster (10 μs) and lower voltages (9 V and -8 V, respectively) due to the higher electric field across the tunneling oxide (Eox) compared to planar devices. Moreover, the results show that increasing the number of stacked nanosheets boosts the drain current but with a negligible effect on the memory window due to the same Eox.

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U2 - 10.1109/SNW56633.2022.9889062

DO - 10.1109/SNW56633.2022.9889062

M3 - Conference contribution

AN - SCOPUS:85141098533

T3 - 2022 IEEE Silicon Nanoelectronics Workshop, SNW 2022

BT - 2022 IEEE Silicon Nanoelectronics Workshop, SNW 2022

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2022 IEEE Silicon Nanoelectronics Workshop, SNW 2022

Y2 - 11 June 2022 through 12 June 2022

ER -

Comparative Analysis of Vertically Stacked Nanosheet FET based SONOS Memory

Abstract

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Access to Document

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