Compact CMOS implementation of a low-power, current-mode programmable cellular neural network

We report on the design and characterization of a full-analog programmable current-mode cellular neural network (CNN) in CMOS technology. In the proposed CNN, a novel cell-core topology, which allows for an easy programming of both feedback and control templates over a wide range of values, including all those required for many signal processing tasks, is employed. The CMOS implementation of this network features both low-power consumption and small-area occupation, making it suitable for the realization of large cell-grid sizes. Device level and Monte Carlo simulations of the network proved that the proposed CNN can be successfully adopted for several applications in both grey-scale and binary image processing tasks. Results from the characterization of a preliminary CNN test-chip (8 × 1 array), intended as a simple demonstrator of the proposed circuit technique, are also reported and discussed.