Challenges in barrier and seed layers characterization of copper technology IC devices

K. Li; E. Er; T. Yeow; D. Tang

Challenges in barrier and seed layers characterization of copper technology IC devices

K. Li^*, E. Er, T. Yeow, D. Tang

^*Corresponding author for this work

Research output: Contribution to conference › Paper › peer-review

1 Scopus citations

Abstract

Ta barrier and Cu seed layer characterization becomes extremely challenging with devices scaling down into 0.13 μm and 90 nm regime. This paper aims at providing a feasible solution for this challenge from both sample preparation and TEM imaging perspectives. Different sample preparation and imaging techniques are compared here.

Original language	English (US)
Pages	263-266
Number of pages	4
State	Published - 2005
Externally published	Yes
Event	12th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2005 - Singapore, Singapore Duration: Jun 27 2005 → Jul 1 2005

Other

Other	12th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2005
Country/Territory	Singapore
City	Singapore
Period	06/27/05 → 07/1/05

ASJC Scopus subject areas

General Engineering

Cite this

@conference{6c028afbf311421e9994259fb3eb3c4f,

title = "Challenges in barrier and seed layers characterization of copper technology IC devices",

abstract = "Ta barrier and Cu seed layer characterization becomes extremely challenging with devices scaling down into 0.13 μm and 90 nm regime. This paper aims at providing a feasible solution for this challenge from both sample preparation and TEM imaging perspectives. Different sample preparation and imaging techniques are compared here.",

author = "K. Li and E. Er and T. Yeow and D. Tang",

year = "2005",

language = "English (US)",

pages = "263--266",

note = "12th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2005 ; Conference date: 27-06-2005 Through 01-07-2005",

}

TY - CONF

T1 - Challenges in barrier and seed layers characterization of copper technology IC devices

AU - Li, K.

AU - Er, E.

AU - Yeow, T.

AU - Tang, D.

PY - 2005

Y1 - 2005

N2 - Ta barrier and Cu seed layer characterization becomes extremely challenging with devices scaling down into 0.13 μm and 90 nm regime. This paper aims at providing a feasible solution for this challenge from both sample preparation and TEM imaging perspectives. Different sample preparation and imaging techniques are compared here.

AB - Ta barrier and Cu seed layer characterization becomes extremely challenging with devices scaling down into 0.13 μm and 90 nm regime. This paper aims at providing a feasible solution for this challenge from both sample preparation and TEM imaging perspectives. Different sample preparation and imaging techniques are compared here.

UR - http://www.scopus.com/inward/record.url?scp=28144440897&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:28144440897

SP - 263

EP - 266

T2 - 12th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2005

Y2 - 27 June 2005 through 1 July 2005

ER -

Challenges in barrier and seed layers characterization of copper technology IC devices

Abstract

Other

ASJC Scopus subject areas

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