Automatic clock domain crossing verification flow for dynamic partial reconfiguration

Islam Ahmed; Hassan Mostafa; Ahmed Nader Mohieldin

doi:10.1109/MWSCAS.2018.8623847

Automatic clock domain crossing verification flow for dynamic partial reconfiguration

Islam Ahmed, Hassan Mostafa, Ahmed Nader Mohieldin

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Dynamic Partial Reconfiguration (DPR) on Field Programmable Gate Arrays (FPGAs) allows some of the logic to be configured while the rest of the logic keeps operating. This kind of designs are called Dynamically Reconfigurable System (DRS) designs, they can operate in multiple modes. The verification of the DRS designs is a complicated task due to the need to verify all the modes of the designs, and the lack of Computer Aided Design (CAD) tools support for DRS designs. In this paper, we propose an automatic Clock Domain Crossing (CDC) verification flow for DRS designs. A Perl utility is implemented which automates the generation of the designs files for each operating mode of the design, generates the script to run CDC analysis on the design, runs a CDC analysis tool, and collates the results in a user-friendly representation for debugging.

Original language	English (US)
Title of host publication	2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)
Publisher	IEEE
Pages	1122-1125
Number of pages	4
ISBN (Print)	9781538673928
DOIs	https://doi.org/10.1109/MWSCAS.2018.8623847
State	Published - Jan 24 2019
Externally published	Yes

Bibliographical note

KAUST Repository Item: Exported on 2022-06-30
Acknowledgements: This research was partially funded by ONE Lab at Cairo University, Zewail City of Science and Technology, and KAUST.
This publication acknowledges KAUST support, but has no KAUST affiliated authors.

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10.1109/MWSCAS.2018.8623847

Cite this

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title = "Automatic clock domain crossing verification flow for dynamic partial reconfiguration",

abstract = "Dynamic Partial Reconfiguration (DPR) on Field Programmable Gate Arrays (FPGAs) allows some of the logic to be configured while the rest of the logic keeps operating. This kind of designs are called Dynamically Reconfigurable System (DRS) designs, they can operate in multiple modes. The verification of the DRS designs is a complicated task due to the need to verify all the modes of the designs, and the lack of Computer Aided Design (CAD) tools support for DRS designs. In this paper, we propose an automatic Clock Domain Crossing (CDC) verification flow for DRS designs. A Perl utility is implemented which automates the generation of the designs files for each operating mode of the design, generates the script to run CDC analysis on the design, runs a CDC analysis tool, and collates the results in a user-friendly representation for debugging.",

author = "Islam Ahmed and Hassan Mostafa and Mohieldin, {Ahmed Nader}",

note = "KAUST Repository Item: Exported on 2022-06-30 Acknowledgements: This research was partially funded by ONE Lab at Cairo University, Zewail City of Science and Technology, and KAUST. This publication acknowledges KAUST support, but has no KAUST affiliated authors.",

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doi = "10.1109/MWSCAS.2018.8623847",

language = "English (US)",

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AU - Ahmed, Islam

AU - Mostafa, Hassan

AU - Mohieldin, Ahmed Nader

N1 - KAUST Repository Item: Exported on 2022-06-30 Acknowledgements: This research was partially funded by ONE Lab at Cairo University, Zewail City of Science and Technology, and KAUST. This publication acknowledges KAUST support, but has no KAUST affiliated authors.

PY - 2019/1/24

Y1 - 2019/1/24

N2 - Dynamic Partial Reconfiguration (DPR) on Field Programmable Gate Arrays (FPGAs) allows some of the logic to be configured while the rest of the logic keeps operating. This kind of designs are called Dynamically Reconfigurable System (DRS) designs, they can operate in multiple modes. The verification of the DRS designs is a complicated task due to the need to verify all the modes of the designs, and the lack of Computer Aided Design (CAD) tools support for DRS designs. In this paper, we propose an automatic Clock Domain Crossing (CDC) verification flow for DRS designs. A Perl utility is implemented which automates the generation of the designs files for each operating mode of the design, generates the script to run CDC analysis on the design, runs a CDC analysis tool, and collates the results in a user-friendly representation for debugging.

AB - Dynamic Partial Reconfiguration (DPR) on Field Programmable Gate Arrays (FPGAs) allows some of the logic to be configured while the rest of the logic keeps operating. This kind of designs are called Dynamically Reconfigurable System (DRS) designs, they can operate in multiple modes. The verification of the DRS designs is a complicated task due to the need to verify all the modes of the designs, and the lack of Computer Aided Design (CAD) tools support for DRS designs. In this paper, we propose an automatic Clock Domain Crossing (CDC) verification flow for DRS designs. A Perl utility is implemented which automates the generation of the designs files for each operating mode of the design, generates the script to run CDC analysis on the design, runs a CDC analysis tool, and collates the results in a user-friendly representation for debugging.

UR - http://hdl.handle.net/10754/679454

UR - https://ieeexplore.ieee.org/document/8623847/

UR - http://www.scopus.com/inward/record.url?scp=85062226969&partnerID=8YFLogxK

U2 - 10.1109/MWSCAS.2018.8623847

DO - 10.1109/MWSCAS.2018.8623847

M3 - Conference contribution

SN - 9781538673928

SP - 1122

EP - 1125

BT - 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)

PB - IEEE

ER -

Automatic clock domain crossing verification flow for dynamic partial reconfiguration

Abstract

Bibliographical note

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