Automatic clock domain crossing verification flow for dynamic partial reconfiguration

Islam Ahmed, Hassan Mostafa, Ahmed Nader Mohieldin

Research output: Chapter in Book/Report/Conference proceedingConference contribution


Dynamic Partial Reconfiguration (DPR) on Field Programmable Gate Arrays (FPGAs) allows some of the logic to be configured while the rest of the logic keeps operating. This kind of designs are called Dynamically Reconfigurable System (DRS) designs, they can operate in multiple modes. The verification of the DRS designs is a complicated task due to the need to verify all the modes of the designs, and the lack of Computer Aided Design (CAD) tools support for DRS designs. In this paper, we propose an automatic Clock Domain Crossing (CDC) verification flow for DRS designs. A Perl utility is implemented which automates the generation of the designs files for each operating mode of the design, generates the script to run CDC analysis on the design, runs a CDC analysis tool, and collates the results in a user-friendly representation for debugging.
Original languageEnglish (US)
Title of host publication2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS)
Number of pages4
ISBN (Print)9781538673928
StatePublished - Jan 24 2019
Externally publishedYes

Bibliographical note

KAUST Repository Item: Exported on 2022-06-30
Acknowledgements: This research was partially funded by ONE Lab at Cairo University, Zewail City of Science and Technology, and KAUST.
This publication acknowledges KAUST support, but has no KAUST affiliated authors.


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