TY - GEN
T1 - Automated design solutions for fully integrated narrow-band low noise amplifiers
AU - Massoud, Yehia
AU - Nieuwoudt, Arthur
AU - Ragheb, Tamer
N1 - Generated from Scopus record by KAUST IRTS on 2022-09-13
PY - 2006/12/1
Y1 - 2006/12/1
N2 - In this paper, we present accurate modeling and automated design solutions for narrow-band low noise amplifiers (LNA) in system-on-chip technology. We develop an analytical circuit model that captures the impact of integrated spiral inductor parasitics and transistor short channel effects. The LNA synthesis methodology leverages deterministic numerical nonlinear optimization techniques to simultaneously optimize both devices and passive components to yield integrated inductor values that are an order of magnitude less than those generated by traditional design techniques. When the optimized LNAs are simulated using Cadence SpectreRF, our methodology yields significant improvement in noise figure and gain over the values obtained using equation-based design techniques. © 2006 IEEE.
AB - In this paper, we present accurate modeling and automated design solutions for narrow-band low noise amplifiers (LNA) in system-on-chip technology. We develop an analytical circuit model that captures the impact of integrated spiral inductor parasitics and transistor short channel effects. The LNA synthesis methodology leverages deterministic numerical nonlinear optimization techniques to simultaneously optimize both devices and passive components to yield integrated inductor values that are an order of magnitude less than those generated by traditional design techniques. When the optimized LNAs are simulated using Cadence SpectreRF, our methodology yields significant improvement in noise figure and gain over the values obtained using equation-based design techniques. © 2006 IEEE.
UR - http://ieeexplore.ieee.org/document/4155271/
UR - http://www.scopus.com/inward/record.url?scp=46249128017&partnerID=8YFLogxK
U2 - 10.1109/IWSOC.2006.348275
DO - 10.1109/IWSOC.2006.348275
M3 - Conference contribution
SN - 1424408989
SP - 109
EP - 114
BT - Proceedings - The 6th IEEE International Workshop on System on Chip for Real Time Applications, IWSOC 2006
ER -