Architecture-aware reconfiguration-centric floorplanning for partial reconfiguration

Kizheppatt Vipin; Suhaib A. Fahmy

doi:10.1007/978-3-642-28365-9_2

Architecture-aware reconfiguration-centric floorplanning for partial reconfiguration

Kizheppatt Vipin, Suhaib A. Fahmy

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

43 Scopus citations

Abstract

Partial reconfiguration (PR) has enabled the adoption of FPGAs in state of the art adaptive applications. Current PR tools require the designer to perform manual floorplanning, which requires knowledge of the physical architecture of FPGAs and an understanding of how to floorplan for optimal performance and area. This has lead to PR remaining a specialist skill and made it less attractive to high level system designers. In this paper we introduce a technique which can be incorporated into the existing tool flow that overcomes the need for manual floorplanning for PR designs. It takes into account overheads generated due to PR as well as the architecture of the latest FPGAs. This results in a floorplan that is efficient for PR systems, where reconfiguration time and area should be minimised. © 2012 Springer-Verlag.

Original language	English (US)
Title of host publication	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Pages	13-25
Number of pages	13
DOIs	https://doi.org/10.1007/978-3-642-28365-9_2
State	Published - Apr 11 2012
Externally published	Yes

Bibliographical note

Generated from Scopus record by KAUST IRTS on 2021-03-16

ASJC Scopus subject areas

Theoretical Computer Science
General Computer Science

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10.1007/978-3-642-28365-9_2

Cite this

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title = "Architecture-aware reconfiguration-centric floorplanning for partial reconfiguration",

abstract = "Partial reconfiguration (PR) has enabled the adoption of FPGAs in state of the art adaptive applications. Current PR tools require the designer to perform manual floorplanning, which requires knowledge of the physical architecture of FPGAs and an understanding of how to floorplan for optimal performance and area. This has lead to PR remaining a specialist skill and made it less attractive to high level system designers. In this paper we introduce a technique which can be incorporated into the existing tool flow that overcomes the need for manual floorplanning for PR designs. It takes into account overheads generated due to PR as well as the architecture of the latest FPGAs. This results in a floorplan that is efficient for PR systems, where reconfiguration time and area should be minimised. {\textcopyright} 2012 Springer-Verlag.",

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PY - 2012/4/11

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N2 - Partial reconfiguration (PR) has enabled the adoption of FPGAs in state of the art adaptive applications. Current PR tools require the designer to perform manual floorplanning, which requires knowledge of the physical architecture of FPGAs and an understanding of how to floorplan for optimal performance and area. This has lead to PR remaining a specialist skill and made it less attractive to high level system designers. In this paper we introduce a technique which can be incorporated into the existing tool flow that overcomes the need for manual floorplanning for PR designs. It takes into account overheads generated due to PR as well as the architecture of the latest FPGAs. This results in a floorplan that is efficient for PR systems, where reconfiguration time and area should be minimised. © 2012 Springer-Verlag.

AB - Partial reconfiguration (PR) has enabled the adoption of FPGAs in state of the art adaptive applications. Current PR tools require the designer to perform manual floorplanning, which requires knowledge of the physical architecture of FPGAs and an understanding of how to floorplan for optimal performance and area. This has lead to PR remaining a specialist skill and made it less attractive to high level system designers. In this paper we introduce a technique which can be incorporated into the existing tool flow that overcomes the need for manual floorplanning for PR designs. It takes into account overheads generated due to PR as well as the architecture of the latest FPGAs. This results in a floorplan that is efficient for PR systems, where reconfiguration time and area should be minimised. © 2012 Springer-Verlag.

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DO - 10.1007/978-3-642-28365-9_2

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BT - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

ER -

Architecture-aware reconfiguration-centric floorplanning for partial reconfiguration

Abstract

Bibliographical note

ASJC Scopus subject areas

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