Architectural Trade-Off Analysis for Accelerating LSTM Network Using Radix- r OBC Scheme

Mohd Tasleem Khan, Hasan Erdem Yantir, Khaled N. Salama, Ahmed Eltawil

Research output: Contribution to journalArticlepeer-review

Abstract

This paper presents architectural trade-off analysis for accelerating two (Type I, II) fixed-point long short-term memory (LSTM) network based on circulant matrix-vector multiplications (MVMs) using radix- r offset binary coding (OBC) scheme. Type I MVM architecture rotates the weights with the proposed modulo-cum interleaver and uses partial product generators (PPGs) with a single generation unit across a column. It is hardware-optimized using a single adder tree through time-multiplexing. Meanwhile, Type II MVM architecture rotates the inputs with the proposed store-cum interleaver and uses single PPGs with a single generation unit across a row. It is time-optimized by unfolding shift-accumulate unit to a shift-add tree followed by pipelining. A new design for element-wise multiplication using radix- r PPG is also presented. Both the designs are extended to their block-circulant variants for certain accuracy requirements. Post-synthesis of Type I and II architectures for a different model, kernel, radix sizes and clock frequencies result in several efficient designs. Compared with the prior scheme, Type I architecture for 128×128 with r=2 on 28 nm FDSOI technology at 800 MHz occupies 32.27% lesser area, consumes 67.89% lesser power at the same throughput, while Type II architecture at the expense of area and power provides 40× higher throughput.
Original languageEnglish (US)
Pages (from-to)1-14
Number of pages14
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
DOIs
StatePublished - Nov 3 2022

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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