TY - GEN
T1 - Analytical modeling of loop self inductance bound for inductance-aware physical synthesis
AU - Mondai, Mosin
AU - Massoud, Yehia
N1 - Generated from Scopus record by KAUST IRTS on 2022-09-13
PY - 2005/12/1
Y1 - 2005/12/1
N2 - An analytical model of loop self Inductance bound has been developed that Is applicable to a wide range of layout geometries commonly encountered In high performance Integrated circuits. When compared with field solver results, the developed model shows an average error of 2.03%. A speedup of more than three orders of magnitude is obtained, enabling our model to be suitable for application in inductance aware physical synthesis. The accurate upper bound of inductance provided by our model can also be used for inductance screening and prelayout inductance estimation. © 2005 IEEE.
AB - An analytical model of loop self Inductance bound has been developed that Is applicable to a wide range of layout geometries commonly encountered In high performance Integrated circuits. When compared with field solver results, the developed model shows an average error of 2.03%. A speedup of more than three orders of magnitude is obtained, enabling our model to be suitable for application in inductance aware physical synthesis. The accurate upper bound of inductance provided by our model can also be used for inductance screening and prelayout inductance estimation. © 2005 IEEE.
UR - http://ieeexplore.ieee.org/document/1594452/
UR - http://www.scopus.com/inward/record.url?scp=33847107722&partnerID=8YFLogxK
U2 - 10.1109/MWSCAS.2005.1594452
DO - 10.1109/MWSCAS.2005.1594452
M3 - Conference contribution
SN - 0780391977
SP - 1721
EP - 1724
BT - Midwest Symposium on Circuits and Systems
ER -